linux-kernel - Re: Query regarding the use of pcie-designware-plat.c file

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Message-ID: <f9bc8a51-7bf8-349d-365b-0493dd811f01@nvidia.com>
Date:   Sun, 20 Jun 2021 19:05:45 +0530
From:   Vidya Sagar <vidyas@...dia.com>
To:     Jon Hunter <jonathanh@...dia.com>,
        Bjorn Helgaas <helgaas@...nel.org>
CC:     <lorenzo.pieralisi@....com>, <bhelgaas@...gle.com>,
        <robh+dt@...nel.org>, <amurray@...goodpenguin.co.uk>,
        <gustavo.pimentel@...opsys.com>, <jingoohan1@...il.com>,
        <Joao.Pinto@...opsys.com>, Thierry Reding <treding@...dia.com>,
        Krishna Thota <kthota@...dia.com>, <linux-pci@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: Query regarding the use of pcie-designware-plat.c file

Given Rob's latest reply, I think Jon's patch addressed the issue in the 
correct way. And IIUC, I think this is how it should be for all Synopsys 
DesignWare implementations unless the implementation really claims that 
it can even work with the generic pcie-designware-plat.c file, otherwise 
it shouldn't contain 'snps,dw-pcie' compatibility string.
IMHO, the addition of 'snps,dw-pcie' along with the respective platform 
specific compatibility string should be strictly restricted.
I think this thread is considered to be concluded at this point.

Thanks,
Vidya Sagar

On 6/16/2021 1:24 PM, Jon Hunter wrote:
> External email: Use caution opening links or attachments
> 
> 
> On 15/06/2021 20:42, Bjorn Helgaas wrote:
>> On Wed, Jun 09, 2021 at 05:54:38PM +0100, Jon Hunter wrote:
>>>
>>> On 09/06/2021 17:30, Bjorn Helgaas wrote:
>>>> On Wed, Jun 09, 2021 at 12:52:37AM +0530, Vidya Sagar wrote:
>>>>> Hi,
>>>>> I would like to know what is the use of pcie-designware-plat.c file. This
>>>>> looks like a skeleton file and can't really work with any specific hardware
>>>>> as such.
>>>>> Some context for this mail thread is, if the config CONFIG_PCIE_DW_PLAT is
>>>>> enabled in a system where a Synopsys DesignWare IP based PCIe controller is
>>>>> present and its configuration is enabled (Ex:- Tegra194 system with
>>>>> CONFIG_PCIE_TEGRA194_HOST enabled), then, it can so happen that the probe of
>>>>> pcie-designware-plat.c called first (because all DWC based PCIe controller
>>>>> nodes have "snps,dw-pcie" compatibility string) and can crash the system.
>>>>
>>>> What's the crash?  If a device claims to be compatible with
>>>> "snps,dw-pcie" and pcie-designware-plat.c claims to know how to
>>>> operate "snps,dw-pcie" devices, it seems like something is wrong.
>>>>
>>>> "snps,dw-pcie" is a generic device type, so pcie-designware-plat.c
>>>> might not know how to operate device-specific details of some of those
>>>> devices, but basic functionality should work and it certainly
>>>> shouldn't crash.
>>>
>>> It is not really a crash but a hang when trying to access the hardware
>>> before it has been properly initialised.
>>
>> This doesn't really answer my question.
>>
>> If the hardware claims to be compatible with "snps,dw-pcie" and a
>> driver knows how to operate "snps,dw-pcie" devices, it should work.
>>
>> If the hardware requires initialization that is not part of the
>> "snps,dw-pcie" programming model, it should not claim to be compatible
>> with "snps,dw-pcie".  Or, if pcie-designware-plat.c is missing some
>> init that *is* part of the programming model, maybe it needs to be
>> enhanced?
> 
> Right and this is exactly why I removed the compatible string
> "snps,dw-pcie" for Tegra194 because it is clear that this does not work
> and hence not compatible.
> 
> Sagar is purely trying to understand if this is case of other devices as
> well or just Tegra194.
> 
> Jon
> 
> --
> nvpublic
>