linux-kernel - [PATCH 4/4] MIPS: CI20: Reduce MSC0 frequency and add second percpu timer for SMP.

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Message-Id: <1624347445-88070-5-git-send-email-zhouyanjie@wanyeetech.com>
Date:   Tue, 22 Jun 2021 15:37:25 +0800
From:   周琰杰 (Zhou Yanjie) 
        <zhouyanjie@...yeetech.com>
To:     tsbogend@...ha.franken.de, paul@...pouillou.net, robh+dt@...nel.org
Cc:     linux-mips@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, dongsheng.qiu@...enic.com,
        aric.pzqi@...enic.com, rick.tyliu@...enic.com,
        sihui.liu@...enic.com, jun.jiang@...enic.com,
        sernia.zhou@...mail.com
Subject: [PATCH 4/4] MIPS: CI20: Reduce MSC0 frequency and add second percpu timer for SMP.

1.On the hardware of CI20 v1, when the MSC0 clock is 50MHz, there is
  a certain probability that the communication with the SD card will
  be abnormal, and the file system will be damaged in severe cases.
  Limiting the maximum MSC0 clock frequency to 25MHz can solve this
  problem.
2.Add a new TCU channel as the percpu timer of core1, this is to
  prepare for the subsequent SMP support. The newly added channel
  will not adversely affect the current single-core state.
3.Adjust the position of TCU node to make it consistent with the
  order in jz4780.dtsi file.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
---
 arch/mips/boot/dts/ingenic/ci20.dts | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 8877c62..58123e0 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -118,11 +118,22 @@
 	assigned-clock-rates = <48000000>;
 };
 
+&tcu {
+	/*
+	 * 750 kHz for the system timers and 3 MHz for the clocksources,
+	 * use channel #0 and #1 for the per cpu system timers, and use
+	 * channel #2 for the clocksource.
+	 */
+	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+					  <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>;
+	assigned-clock-rates = <750000>, <750000>, <3000000>, <3000000>;
+};
+
 &mmc0 {
 	status = "okay";
 
 	bus-width = <4>;
-	max-frequency = <50000000>;
+	max-frequency = <25000000>;
 
 	pinctrl-names = "default";
 	pinctrl-0 = <&pins_mmc0>;
@@ -522,13 +533,3 @@
 		bias-disable;
 	};
 };
-
-&tcu {
-	/*
-	 * 750 kHz for the system timer and 3 MHz for the clocksource,
-	 * use channel #0 for the system timer, #1 for the clocksource.
-	 */
-	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
-					  <&tcu TCU_CLK_OST>;
-	assigned-clock-rates = <750000>, <3000000>, <3000000>;
-};
-- 
2.7.4