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Message-ID: <5a1534346e524b3808c11c6a4d224c86@codeaurora.org>
Date: Thu, 01 Jul 2021 01:27:33 +0530
From: Sibi Sankar <sibis@...eaurora.org>
To: Matthias Kaehlcke <mka@...omium.org>
Cc: bjorn.andersson@...aro.org, robh+dt@...nel.org, will@...nel.org,
saiprakash.ranjan@...eaurora.org, ohad@...ery.com,
agross@...nel.org, mathieu.poirier@...aro.org,
robin.murphy@....com, joro@...tes.org, p.zabel@...gutronix.de,
linux-arm-msm@...r.kernel.org, linux-remoteproc@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, evgreen@...omium.org,
dianders@...omium.org, swboyd@...omium.org
Subject: Re: [PATCH 3/9] dt-bindings: remoteproc: qcom: Add Q6V5 Modem PIL
binding
On 2021-06-26 05:13, Matthias Kaehlcke wrote:
> On Fri, Jun 25, 2021 at 01:17:32AM +0530, Sibi Sankar wrote:
>> Add a new modem compatible string for QTI SC7280 SoCs and introduce
>> the
>> "qcom,ext-regs" and "qcom,qaccept-regs" bindings needed by the modem
>> sub-system running on SC7280 SoCs.
>>
>> Signed-off-by: Sibi Sankar <sibis@...eaurora.org>
>> ---
>> .../devicetree/bindings/remoteproc/qcom,q6v5.txt | 32
>> ++++++++++++++++++++--
>> 1 file changed, 30 insertions(+), 2 deletions(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
>> b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
>> index 494257010629..d802e57701b8 100644
>> --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
>> +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
>>
>> ...
>>
>> @@ -208,6 +218,24 @@ For the compatible strings below the following
>> phandle references are required:
>> by the offset within syscon for conn_box_spare0 register
>> used by the modem sub-system running on SC7180 SoC.
>>
>> +For the compatible strings below the following phandle references are
>> required:
>> + "qcom,sc7280-mss-pil"
>> +- qcom,ext-regs:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: two phandles reference to syscons representing TCSR_REG
>> and
>
> s/phandles reference/phandle references/
>
>> + TCSR register space followed by the two offset within the
>> syscon
>
> s/offset/offsets/
>
>> + to force_clk_en/rscc_disable and axim1_clk_off/crypto_clk_off
>> + registers respectively.
will fix ^^ in the re-spin.
--
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