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Message-ID: <b0e381cb536dceeda2f0ac9ee3dcd16ddeb0c961.camel@pengutronix.de>
Date: Fri, 09 Jul 2021 11:55:03 +0200
From: Lucas Stach <l.stach@...gutronix.de>
To: Robin Gong <yibin.gong@....com>, vkoul@...nel.org,
mark.rutland@....com, broonie@...nel.org, robh+dt@...nel.org,
catalin.marinas@....com, will.deacon@....com, shawnguo@...nel.org,
festevam@...il.com, s.hauer@...gutronix.de,
martin.fuzzey@...wbird.group, u.kleine-koenig@...gutronix.de,
dan.j.williams@...el.com, matthias.schiffer@...tq-group.com,
frieder.schrempf@...tron.de, m.felsch@...gutronix.de,
xiaoning.wang@....com
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-spi@...r.kernel.org, linux-imx@....com,
kernel@...gutronix.de, dmaengine@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v14 11/12] dmaengine: imx-sdma: add uart rom script
Am Mittwoch, dem 07.04.2021 um 23:30 +0800 schrieb Robin Gong:
> For the compatibility of NXP internal legacy kernel before 4.19 which
> is based on uart ram script and upstreaming kernel based on uart rom
> script, add both uart ram/rom script in latest sdma firmware. By default
> uart rom script used.
> Besides, add two multi-fifo scripts for SAI/PDM on i.mx8m/8mm and add
> back qspi script miss for v4(i.mx7d/8m/8mm family, but v3 is for i.mx6).
>
> rom script:
> uart_2_mcu_addr
> uartsh_2_mcu_addr /* through spba bus */
> am script:
> uart_2_mcu_ram_addr
> uartsh_2_mcu_ram_addr /* through spba bus */
>
> Please get latest sdma firmware from the below and put them into the path
> (/lib/firmware/imx/sdma/):
> https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
> /tree/imx/sdma
>
> Signed-off-by: Robin Gong <yibin.gong@....com>
> Acked-by: Vinod Koul <vkoul@...nel.org>
Reviewed-by: Lucas Stach <l.stach@...gutronix.de>
> ---
> drivers/dma/imx-sdma.c | 17 +++++++++++++++--
> include/linux/platform_data/dma-imx-sdma.h | 8 ++++++--
> 2 files changed, 21 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index af85116..9519b41 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -1696,8 +1696,8 @@ static void sdma_issue_pending(struct dma_chan *chan)
>
> #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
> #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
> -#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
> -#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
> +#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 45
> +#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 46
>
> static void sdma_add_scripts(struct sdma_engine *sdma,
> const struct sdma_script_start_addrs *addr)
> @@ -1721,6 +1721,19 @@ static void sdma_add_scripts(struct sdma_engine *sdma,
> for (i = 0; i < sdma->script_number; i++)
> if (addr_arr[i] > 0)
> saddr_arr[i] = addr_arr[i];
> +
> + /*
> + * get uart_2_mcu_addr/uartsh_2_mcu_addr rom script specially because
> + * they are now replaced by uart_2_mcu_ram_addr/uartsh_2_mcu_ram_addr
> + * to be compatible with legacy freescale/nxp sdma firmware, and they
> + * are located in the bottom part of sdma_script_start_addrs which are
> + * beyond the SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1.
> + */
> + if (addr->uart_2_mcu_addr)
> + sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_addr;
> + if (addr->uartsh_2_mcu_addr)
> + sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_addr;
> +
> }
>
> static void sdma_load_firmware(const struct firmware *fw, void *context)
> diff --git a/include/linux/platform_data/dma-imx-sdma.h b/include/linux/platform_data/dma-imx-sdma.h
> index 725602d..91dac29 100644
> --- a/include/linux/platform_data/dma-imx-sdma.h
> +++ b/include/linux/platform_data/dma-imx-sdma.h
> @@ -20,12 +20,12 @@ struct sdma_script_start_addrs {
> s32 per_2_firi_addr;
> s32 mcu_2_firi_addr;
> s32 uart_2_per_addr;
> - s32 uart_2_mcu_addr;
> + s32 uart_2_mcu_ram_addr;
> s32 per_2_app_addr;
> s32 mcu_2_app_addr;
> s32 per_2_per_addr;
> s32 uartsh_2_per_addr;
> - s32 uartsh_2_mcu_addr;
> + s32 uartsh_2_mcu_ram_addr;
> s32 per_2_shp_addr;
> s32 mcu_2_shp_addr;
> s32 ata_2_mcu_addr;
> @@ -52,6 +52,10 @@ struct sdma_script_start_addrs {
> s32 zcanfd_2_mcu_addr;
> s32 zqspi_2_mcu_addr;
> s32 mcu_2_ecspi_addr;
> + s32 mcu_2_sai_addr;
> + s32 sai_2_mcu_addr;
> + s32 uart_2_mcu_addr;
> + s32 uartsh_2_mcu_addr;
> /* End of v3 array */
> s32 mcu_2_zqspi_addr;
> /* End of v4 array */
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