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Date: Tue, 13 Jul 2021 20:47:56 -0600
From: Rob Herring <robh@...nel.org>
To: shruthi.sanil@...el.com
Cc: daniel.lezcano@...aro.org, tglx@...utronix.de,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
andriy.shevchenko@...ux.intel.com, kris.pan@...ux.intel.com,
mgross@...ux.intel.com, srikanth.thokala@...el.com,
lakshmi.bai.raja.subramanian@...el.com,
mallikarjunappa.sangannavar@...el.com
Subject: Re: [PATCH v4 1/2] dt-bindings: timer: Add bindings for Intel Keem
Bay SoC Timer
On Mon, Jun 28, 2021 at 11:44:09AM +0530, shruthi.sanil@...el.com wrote:
> From: Shruthi Sanil <shruthi.sanil@...el.com>
>
> Add Device Tree bindings for the Timer IP, which can be used as
> clocksource and clockevent device in the Intel Keem Bay SoC.
>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@...el.com>
> Signed-off-by: Shruthi Sanil <shruthi.sanil@...el.com>
> ---
> .../bindings/timer/intel,keembay-timer.yaml | 170 ++++++++++++++++++
> 1 file changed, 170 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> new file mode 100644
> index 000000000000..24c149a4d220
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
> @@ -0,0 +1,170 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel Keem Bay SoC Timers
> +
> +maintainers:
> + - Shruthi Sanil <shruthi.sanil@...el.com>
> +
> +description: |
> + The Intel Keem Bay timer driver supports clocksource and clockevent
> + features for the timer IP used in Intel Keembay SoC.
> + The timer block supports 1 free running counter and 8 timers.
> + The free running counter can be used as a clocksouce and
> + the timers can be used as clockevent. Each timer is capable of
> + generating inividual interrupt.
clockevent and clocksource are Linuxisms. Don't use them in bindings.
> + Both the features are enabled through the timer general config register.
> +
> + The parent node represents the common general configuration details and
> + the child nodes represents the counter and timers.
I don't think all the child nodes are necessary. Are the counters and
timers configurable (say on another SoC)? If not, then a single node
here would suffice.
> +
> +properties:
> + reg:
> + description: General configuration register address and length.
> + maxItems: 1
> +
> + ranges: true
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> +required:
> + - reg
> + - ranges
> + - "#address-cells"
> + - "#size-cells"
> +
> +patternProperties:
> + "^counter@[0-9a-f]+$":
> + type: object
> + description: Properties for Intel Keem Bay counter
> +
> + properties:
> + compatible:
> + enum:
> + - intel,keembay-counter
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + required:
> + - compatible
> + - reg
> + - clocks
> +
> + "^timer@[0-9a-f]+$":
> + type: object
> + description: Properties for Intel Keem Bay timer
> +
> + properties:
> + compatible:
> + enum:
> + - intel,keembay-timer
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #define KEEM_BAY_A53_TIM
> +
> + soc {
> + #address-cells = <0x2>;
> + #size-cells = <0x2>;
> +
> + gpt@...31000 {
> + reg = <0x0 0x20331000 0x0 0xc>;
> + ranges = <0x0 0x0 0x20330000 0xF0>;
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> +
> + counter@...300e8 {
The unit address here is wrong. Should be 'e8'.
> + compatible = "intel,keembay-counter";
> + reg = <0xe8 0x8>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@...30010 {
> + compatible = "intel,keembay-timer";
> + reg = <0x10 0xc>;
> + interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@...30020 {
> + compatible = "intel,keembay-timer";
> + reg = <0x20 0xc>;
> + interrupts = <GIC_SPI 0x4 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@...30030 {
> + compatible = "intel,keembay-timer";
> + reg = <0x30 0xc>;
> + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@...30040 {
> + compatible = "intel,keembay-timer";
> + reg = <0x40 0xc>;
> + interrupts = <GIC_SPI 0x6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@...30050 {
> + compatible = "intel,keembay-timer";
> + reg = <0x50 0xc>;
> + interrupts = <GIC_SPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@...30060 {
> + compatible = "intel,keembay-timer";
> + reg = <0x60 0xc>;
> + interrupts = <GIC_SPI 0x8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@...30070 {
> + compatible = "intel,keembay-timer";
> + reg = <0x70 0xc>;
> + interrupts = <GIC_SPI 0x9 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> +
> + timer@...30080 {
> + compatible = "intel,keembay-timer";
> + reg = <0x80 0xc>;
> + interrupts = <GIC_SPI 0xa IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
> + };
> + };
> + };
> +
> +...
> --
> 2.17.1
>
>
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