lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 14 Jul 2021 12:31:25 +0300
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Jiri Slaby <jirislaby@...nel.org>
Cc:     linux-serial@...r.kernel.org, linux-kernel@...r.kernel.org,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Ralf Ramsauer <ralf.ramsauer@...-regensburg.de>
Subject: Re: [PATCH v1 3/4] serial: 8250_pci: Always try MSI/MSI-X

On Wed, Jul 14, 2021 at 09:58:52AM +0200, Jiri Slaby wrote:
> On 14. 07. 21, 8:54, Jiri Slaby wrote:
> > > @@ -3994,14 +3982,9 @@ pciserial_init_ports(struct pci_dev *dev,
> > > const struct pciserial_board *board)
> > >       if (board->flags & FL_NOIRQ) {
> > >           uart.port.irq = 0;
> > >       } else {
> > > -        if (pci_match_id(pci_use_msi, dev)) {
> > > -            dev_dbg(&dev->dev, "Using MSI(-X) interrupts\n");
> > > -            pci_set_master(dev);
> > > -            rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
> > > -        } else {
> > > -            dev_dbg(&dev->dev, "Using legacy interrupts\n");
> > > -            rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
> > > -        }
> > > +        pci_set_master(dev);
> > 
> > But bus mastering is not about MSIs. I *think* it's still OK, but you
> > need to document that in the commit log too.
> > 
> > Actually, why the commit which added this code turns on bus mastering?
> 
> Forget about this line, I wasn't woken enough. Of course, MSI (writes) to
> bus need bus mastering.

Yes.

> In any case, I'm still not sure what happens to devices which do not support
> MSI if we enable mastering on them?

If they support bus mastering, it means that device may be an arbiter on the
bus and initiate messages over it by its own. I'm not sure any of the existing
UARTs take advantage of bus mastering for anything than MSI delivery.

-- 
With Best Regards,
Andy Shevchenko


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ