linux-kernel - Re: [PATCH v1] arm64: dts: imx8qm: added System MMU

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Thu, 15 Jul 2021 10:46:44 +0200
From:   Oliver Graute <oliver.graute@...oconnector.com>
To:     Robin Murphy <robin.murphy@....com>
Cc:     shawnguo@...nel.org, devicetree@...r.kernel.org,
        aisheng.dong@....com, fabio.estevam@....com,
        Rob Herring <robh+dt@...nel.org>,
        Sascha Hauer <kernel@...gutronix.de>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        NXP Linux Team <linux-imx@....com>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1] arm64: dts: imx8qm: added System MMU

On 14/07/21, Robin Murphy wrote:
> On 2021-07-14 13:09, Oliver Graute wrote:
> > added node for System MMU
> 
> Note that it's a bit of a dangerous game to enable an SMMU without the
> complete Stream ID topology for *all* its upstream devices also described,
> since CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT will ruin peoples' day. It
> might be more polite to add it in a disabled state until every "iommus"
> property has been filled in, so that people who do want to play with it for
> specific devices in the meantime can easily just flip the status (while
> taking the necessary precautions), but people who don't care won't be
> inadvertently affected regardless of their kernel config. I'm assuming an
> SMMU with 32 contexts has more than a single USB controller behind it...

thx for the explanation. So I will set this node to disabled state in
next version of this patch.
> 
> >   	};
> > +	smmu: iommu@...00000 {
> > +		compatible = "arm,mmu-500";
> > +		interrupt-parent = <&gic>;
> > +		reg = <0 0x51400000 0 0x40000>;
> > +		#global-interrupts = <1>;
> > +		#iommu-cells = <2>;
> > +		interrupts = <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > +			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
		status = "disabled";
> > +	};

Best regards,

Oliver