Message-ID: <CAATdQgDOGW7nudDoR5UPbax+d3e9omhPstrNd_FCPLd+96ZC9w@mail.gmail.com>
Date:   Wed, 21 Jul 2021 20:54:00 +0800
From:   Ikjoon Jang <ikjn@...omium.org>
To:     Yong Wu <yong.wu@...iatek.com>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        Rob Herring <robh+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Krzysztof Kozlowski <krzk@...nel.org>,
        Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
        Robin Murphy <robin.murphy@....com>,
        Tomasz Figa <tfiga@...omium.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@...ts.infradead.org>,
        srv_heupstream <srv_heupstream@...iatek.com>,
        open list <linux-kernel@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-arm-kernel@...ts.infradead.org>,
        iommu@...ts.linux-foundation.org, youlin.pei@...iatek.com,
        anan.sun@...iatek.com, ming-fan.chen@...iatek.com,
        yi.kuo@...iatek.com, anthony.huang@...iatek.com
Subject: Re: [PATCH v2 10/11] memory: mtk-smi: mt8195: Add initial setting for smi-common

On Thu, Jul 15, 2021 at 8:25 PM Yong Wu <yong.wu@...iatek.com> wrote:
>
> To improve the performance, add initial setting for smi-common.
> some register use some fix setting(suggested from DE).
>
> Signed-off-by: Yong Wu <yong.wu@...iatek.com>
> ---
>  drivers/memory/mtk-smi.c | 42 ++++++++++++++++++++++++++++++++++++----
>  1 file changed, 38 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> index 3c288716a378..c52bf02458ff 100644
> --- a/drivers/memory/mtk-smi.c
> +++ b/drivers/memory/mtk-smi.c
> @@ -18,11 +18,19 @@
>  #include <dt-bindings/memory/mtk-memory-port.h>
>
>  /* SMI COMMON */
> +#define SMI_L1LEN                      0x100
> +
>  #define SMI_BUS_SEL                    0x220
>  #define SMI_BUS_LARB_SHIFT(larbid)     ((larbid) << 1)
>  /* All are MMU0 defaultly. Only specialize mmu1 here. */
>  #define F_MMU1_LARB(larbid)            (0x1 << SMI_BUS_LARB_SHIFT(larbid))
>
> +#define SMI_M4U_TH                     0x234
> +#define SMI_FIFO_TH1                   0x238
> +#define SMI_FIFO_TH2                   0x23c
> +#define SMI_DCM                                0x300
> +#define SMI_DUMMY                      0x444
> +
>  /* SMI LARB */
>
>  /* Below are about mmu enable registers, they are different in SoCs */
> @@ -58,6 +66,13 @@
>         (_id << 8 | _id << 10 | _id << 12 | _id << 14); \
>  })
>
> +#define SMI_COMMON_INIT_REGS_NR                6
> +
> +struct mtk_smi_reg_pair {
> +       unsigned int            offset;
> +       u32                     value;
> +};
> +
>  enum mtk_smi_type {
>         MTK_SMI_GEN1,
>         MTK_SMI_GEN2,           /* gen2 smi common */
> @@ -74,6 +89,8 @@ static const char * const mtk_smi_larb_clks_optional[] = {"gals"};
>  struct mtk_smi_common_plat {
>         enum mtk_smi_type       type;
>         u32                     bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
> +
> +       const struct mtk_smi_reg_pair   *init;
>  };
>
>  struct mtk_smi_larb_gen {
> @@ -409,6 +426,15 @@ static struct platform_driver mtk_smi_larb_driver = {
>         }
>  };
>
> +static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = {
> +       {SMI_L1LEN, 0xb},
> +       {SMI_M4U_TH, 0xe100e10},
> +       {SMI_FIFO_TH1, 0x506090a},
> +       {SMI_FIFO_TH2, 0x506090a},
> +       {SMI_DCM, 0x4f1},
> +       {SMI_DUMMY, 0x1},
> +};
> +
>  static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
>         .type     = MTK_SMI_GEN1,
>  };
> @@ -439,11 +465,13 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = {
>         .type     = MTK_SMI_GEN2,
>         .bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) |
>                     F_MMU1_LARB(7),
> +       .init     = mtk_smi_common_mt8195_init,
>  };
>
>  static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = {
>         .type     = MTK_SMI_GEN2,
>         .bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
> +       .init     = mtk_smi_common_mt8195_init,
>  };
>
>  static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = {
> @@ -530,15 +558,21 @@ static int mtk_smi_common_remove(struct platform_device *pdev)
>  static int __maybe_unused mtk_smi_common_resume(struct device *dev)
>  {
>         struct mtk_smi *common = dev_get_drvdata(dev);
> -       u32 bus_sel = common->plat->bus_sel;
> -       int ret;
> +       const struct mtk_smi_reg_pair *init = common->plat->init;
> +       u32 bus_sel = common->plat->bus_sel; /* default is 0 */
> +       int ret, i;
>
>         ret = clk_bulk_prepare_enable(common->clk_num, common->clks);
>         if (ret)
>                 return ret;
>
> -       if (common->plat->type == MTK_SMI_GEN2 && bus_sel)
> -               writel(bus_sel, common->base + SMI_BUS_SEL);
> +       if (common->plat->type != MTK_SMI_GEN2)
> +               return 0;
> +
> +       for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++)
> +               writel_relaxed(init[i].value, common->base + init[i].offset);

I'm not sure this array for register settings could be applied to other
platforms in future or only applied to mt8195. If it's only for mt8195,
I think taking callback function instead of mtk_smi_reg_pair[] as init member
would be better:

if (common->plat->init)
    common->plat->init(...);

> +
> +       writel(bus_sel, common->base + SMI_BUS_SEL);
>         return 0;
>  }
>
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

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