linux-kernel - Re: [v14 06/21] clk: mediatek: Fix asymmetrical PLL enable and disable control

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Message-ID: <162740849051.2368309.17691414587415743961@swboyd.mtv.corp.google.com>
Date:   Tue, 27 Jul 2021 10:54:50 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Chun-Jie Chen <chun-jie.chen@...iatek.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Nicolas Boichat <drinkcat@...omium.org>,
        Rob Herring <robh+dt@...nel.org>
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-mediatek@...ts.infradead.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, srv_heupstream@...iatek.com,
        Project_Global_Chrome_Upstream_Group@...iatek.com,
        Weiyi Lu <weiyi.lu@...iatek.com>,
        Chun-Jie Chen <chun-jie.chen@...iatek.com>
Subject: Re: [v14 06/21] clk: mediatek: Fix asymmetrical PLL enable and disable control

Quoting Chun-Jie Chen (2021-07-26 03:57:04)
> In fact, the en_mask is a combination of divider enable mask
> and pll enable bit(bit0).
> Before this patch, we enabled both divider mask and bit0 in prepare(),
> but only cleared the bit0 in unprepare().
> In the future, we hope en_mask will only be used as divider enable mask.
> The enable register(CON0) will be set in 2 steps:
> first is divider mask, and then bit0 during prepare(), and vice versa.
> But considering backward compatibility, at this stage we allow en_mask
> to be a combination or a pure divider enable mask.
> And then we will make en_mask a pure divider enable mask in another
> following patch series.
> 
> Reviewed-by: Ikjoon Jang <ikjn@...omium.org>
> Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@...iatek.com>
> ---

Applied to clk-next