linux-kernel - Re: [v14 07/21] clk: mediatek: Add configurable enable control to mtk_pll

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Date:   Tue, 27 Jul 2021 10:55:00 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Chun-Jie Chen <chun-jie.chen@...iatek.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Nicolas Boichat <drinkcat@...omium.org>,
        Rob Herring <robh+dt@...nel.org>
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-mediatek@...ts.infradead.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, srv_heupstream@...iatek.com,
        Project_Global_Chrome_Upstream_Group@...iatek.com,
        Weiyi Lu <weiyi.lu@...iatek.com>,
        Chun-Jie Chen <chun-jie.chen@...iatek.com>
Subject: Re: [v14 07/21] clk: mediatek: Add configurable enable control to mtk_pll_data

Quoting Chun-Jie Chen (2021-07-26 03:57:05)
> In all MediaTek PLL design, bit0 of CON0 register is always
> the enable bit.
> However, there's a special case of usbpll on MT8192.
> The enable bit of usbpll is moved to bit2 of other register.
> Add configurable en_reg and pll_en_bit for enable control or
> default 0 where pll data are static variables.
> Hence, CON0_BASE_EN could also be removed.
> And there might have another special case on other chips,
> the enable bit is still on CON0 register but not at bit0.
> 
> Reviewed-by: Ikjoon Jang <ikjn@...omium.org>
> Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@...iatek.com>
> ---

Applied to clk-next