linux-kernel - Re: [PATCH v3 1/2] arm64: dts: qcom: sc7280: Add gpu support

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Message-ID: <CAF6AEGv9G99YqEixdUZCLxEgXX1+EqcjgQP-v5CCuj64sv_bTA@mail.gmail.com>
Date:   Thu, 29 Jul 2021 10:35:32 -0700
From:   Rob Clark <robdclark@...il.com>
To:     Stephen Boyd <swboyd@...omium.org>
Cc:     Akhil P Oommen <akhilpo@...eaurora.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Manaf Meethalavalappu Pallikunhi <manafm@...eaurora.org>,
        OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS 
        <devicetree@...r.kernel.org>, Rob Herring <robh+dt@...nel.org>,
        dri-devel <dri-devel@...ts.freedesktop.org>,
        freedreno <freedreno@...ts.freedesktop.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        Jordan Crouse <jordan@...micpenguin.net>,
        Douglas Anderson <dianders@...omium.org>,
        Matthias Kaehlcke <mka@...omium.org>,
        Jonathan Marek <jonathan@...ek.ca>,
        Andy Gross <agross@...nel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 1/2] arm64: dts: qcom: sc7280: Add gpu support

On Thu, Jul 29, 2021 at 10:19 AM Stephen Boyd <swboyd@...omium.org> wrote:
>
> Quoting Akhil P Oommen (2021-07-28 04:54:01)
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index 029723a..c88f366 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > @@ -592,6 +593,85 @@
> >                         qcom,bcm-voters = <&apps_bcm_voter>;
> >                 };
> >
> > +               gpu@...0000 {
> > +                       compatible = "qcom,adreno-635.0", "qcom,adreno";
> > +                       #stream-id-cells = <16>;
> > +                       reg = <0 0x03d00000 0 0x40000>,
> > +                             <0 0x03d9e000 0 0x1000>,
> > +                             <0 0x03d61000 0 0x800>;
> > +                       reg-names = "kgsl_3d0_reg_memory",
> > +                                   "cx_mem",
> > +                                   "cx_dbgc";
> > +                       interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> > +                       iommus = <&adreno_smmu 0 0x401>;
> > +                       operating-points-v2 = <&gpu_opp_table>;
> > +                       qcom,gmu = <&gmu>;
> > +                       interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
> > +                       interconnect-names = "gfx-mem";
> > +
> > +                       gpu_opp_table: opp-table {
> > +                               compatible = "operating-points-v2";
> > +
> > +                               opp-550000000 {
> > +                                       opp-hz = /bits/ 64 <550000000>;
> > +                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> > +                                       opp-peak-kBps = <6832000>;
> > +                               };
> > +
> > +                               opp-450000000 {
>
> Why is 450000000 after 550000000? Is it on purpose? If not intended
> please sort by frequency.

We've used descending order, at least for gpu opp table, on other
gens, fwiw.. not sure if that just means we were doing it wrong
previously

BR,
-R

>
> > +                                       opp-hz = /bits/ 64 <450000000>;
> > +                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> > +                                       opp-peak-kBps = <4068000>;
> > +                               };
> > +
> > +                               opp-315000000 {
> > +                                       opp-hz = /bits/ 64 <315000000>;
> > +                                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> > +                                       opp-peak-kBps = <1804000>;
> > +                               };
> > +                       };
> > +               };
> > +