linux-kernel - Re: [PATCH v3 1/2] dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver

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Date:   Fri, 30 Jul 2021 11:05:43 +0200
From:   Linus Walleij <linus.walleij@...aro.org>
To:     "D, Lakshmi Sowjanya" <lakshmi.sowjanya.d@...el.com>
Cc:     "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        "Raja Subramanian, Lakshmi Bai" 
        <lakshmi.bai.raja.subramanian@...el.com>,
        "Saha, Tamal" <tamal.saha@...el.com>
Subject: Re: [PATCH v3 1/2] dt-bindings: pinctrl: Add bindings for Intel
 Keembay pinctrl driver

Hi Lakshmi,

sorry for slow review.

Since this is one of those "Intel but Arm" things I don't know how
Andy feels about picking up the patch to his Intel pinctrl tree
(I think we discussed it in the past) so I need to know how to handle
this. It'd be great if Andy queues "all Intel stuff" but I don't want
to force unfamiliar stuff on him either.

Andy? Do you pick this (when finished) or should I?

On Fri, Jul 16, 2021 at 6:27 PM <lakshmi.sowjanya.d@...el.com> wrote:

> +        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

Did we discuss this before? Are these hierarchical or does these IRQs
map to more than one GPIO line?

If they are hieararchical then the driver should just pick the lines
in hierarchy from the parent with no data in the driver, but if one
of these IRQ lines maps to more than one GPIO line they should
be like this.

Yours,
Linus Walleij