linux-kernel - Re: [PATCH v3 2/2] pinctrl: Add Intel Keem Bay pinctrl driver

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Message-ID: <CACRpkdbv77hjJ91h3fuLSYbpT+Yxd4X8_S7F+NsUw+QsKXN3Ww@mail.gmail.com>
Date:   Fri, 30 Jul 2021 11:13:34 +0200
From:   Linus Walleij <linus.walleij@...aro.org>
To:     "D, Lakshmi Sowjanya" <lakshmi.sowjanya.d@...el.com>
Cc:     "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        "Raja Subramanian, Lakshmi Bai" 
        <lakshmi.bai.raja.subramanian@...el.com>,
        "Saha, Tamal" <tamal.saha@...el.com>
Subject: Re: [PATCH v3 2/2] pinctrl: Add Intel Keem Bay pinctrl driver

Hi Lakshmi,

On Fri, Jul 16, 2021 at 6:27 PM <lakshmi.sowjanya.d@...el.com> wrote:

> +       /*
> +        * Each Interrupt line can be shared by up to 4 GPIO pins. Enable bit
> +        * and input values were checked to identify the source of the
> +        * Interrupt. The checked enable bit positions are 7, 15, 23 and 31.
> +        */
> +       for_each_set_clump8(bit, clump, &reg, BITS_PER_TYPE(typeof(reg))) {
> +               pin = clump & ~KEEMBAY_GPIO_IRQ_ENABLE;
> +               val = keembay_read_pin(kpc->base0 + KEEMBAY_GPIO_DATA_IN, pin);
> +               kmb_irq = irq_linear_revmap(gc->irq.domain, pin);
> +
> +               /* Checks if the interrupt is enabled */
> +               if (val && (clump & KEEMBAY_GPIO_IRQ_ENABLE))
> +                       generic_handle_irq(kmb_irq);
> +       }

Aha there it is. "Half-hierarchical" with one IRQ handling 4 lines.

OK we can't do any better than this so this and the bindings
look fine.

I need to know how Andy think about merging, and then there is
an uninitialized ret in the mail from Dan Carpenter look into that
too.

In any case with minor nits fixed:
Reviewed-by: Linus Walleij <linus.walleij@...aro.org>

Yours,
Linus Walleij