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Message-ID: <CACRpkdZJaoQEJsAqrrAxWcpgx6J0OGoc_CkP0kUdNe-RPkRvqA@mail.gmail.com>
Date:   Fri, 30 Jul 2021 11:15:01 +0200
From:   Linus Walleij <linus.walleij@...aro.org>
To:     "D, Lakshmi Sowjanya" <lakshmi.sowjanya.d@...el.com>
Cc:     "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        "Raja Subramanian, Lakshmi Bai" 
        <lakshmi.bai.raja.subramanian@...el.com>,
        "Saha, Tamal" <tamal.saha@...el.com>
Subject: Re: [PATCH v3 1/2] dt-bindings: pinctrl: Add bindings for Intel
 Keembay pinctrl driver

On Fri, Jul 16, 2021 at 6:27 PM <lakshmi.sowjanya.d@...el.com> wrote:

> From: Lakshmi Sowjanya D <lakshmi.sowjanya.d@...el.com>
>
> Add Device Tree bindings documentation for Intel Keem Bay
> SoC's pin controller.
> Add entry for INTEL Keem Bay pinctrl driver in MAINTAINERS file
>
> Acked-by: Mark Gross <mgross@...ux.intel.com>
> Co-developed-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@...el.com>
> Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@...el.com>
> Co-developed-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@...el.com>
> Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@...el.com>
> Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@...el.com>
(...)
> +  interrupts:
> +    description:
> +      Specifies the interrupt lines to be used by the controller.
> +    maxItems: 8

Write here that each interrupt is shared by up to 4 GPIO lines.

With that:
Reviewed-by: Linus Walleij <linus.walleij@...aro.org>

Yours,
Linus Walleij

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