Message-ID: <CAPLW+4nY=hozOR+B_0sPZODrk9PXaXg+NB-9pVhDbAjEy7yjhg@mail.gmail.com>
Date:   Thu, 5 Aug 2021 00:30:34 +0300
From:   Sam Protsenko <semen.protsenko@...aro.org>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
Cc:     Marc Zyngier <maz@...nel.org>,
        Sylwester Nawrocki <s.nawrocki@...sung.com>,
        Chanwoo Choi <cw00.choi@...sung.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Tomasz Figa <tomasz.figa@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Jiri Slaby <jirislaby@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Charles Keepax <ckeepax@...nsource.wolfsonmicro.com>,
        Ryu Euiyoul <ryu.real@...sung.com>,
        Tom Gall <tom.gall@...aro.org>,
        Sumit Semwal <sumit.semwal@...aro.org>,
        John Stultz <john.stultz@...aro.org>,
        Amit Pundir <amit.pundir@...aro.org>,
        devicetree <devicetree@...r.kernel.org>,
        linux-arm Mailing List <linux-arm-kernel@...ts.infradead.org>,
        linux-clk <linux-clk@...r.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linux Samsung SOC <linux-samsung-soc@...r.kernel.org>,
        "open list:SERIAL DRIVERS" <linux-serial@...r.kernel.org>
Subject: Re: [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support

On Wed, 4 Aug 2021 at 21:36, Krzysztof Kozlowski
<krzysztof.kozlowski@...onical.com> wrote:
>
> On 04/08/2021 16:39, Sam Protsenko wrote:
> > Hi Marc,
> >
> > On Fri, 30 Jul 2021 at 19:50, Marc Zyngier <maz@...nel.org> wrote:
> >>
> >> On 2021-07-30 15:49, Sam Protsenko wrote:
> >>> Samsung Exynos850 is ARMv8-based mobile-oriented SoC.
> >>>
> >>> Features:
> >>>  * CPU: Cortex-A55 Octa (8 cores), up to 2 GHz
> >>>  * Memory interface: LPDDR4/4x 2 channels (12.8 GB/s)
> >>>  * SD/MMC: SD 3.0, eMMC5.1 DDR 8-bit
> >>>  * Modem: 4G LTE, 3G, GSM/GPRS/EDGE
> >>>  * RF: Quad GNSS, WiFi 5 (802.11ac), Bluetooth 5.0
> >>>  * GPU: Mali-G52 MP1
> >>>  * Codec: 1080p 60fps H64, HEVC, JPEG HW Codec
> >>>  * Display: Full HD+ (2520x1080)@60fps LCD
> >>>  * Camera: 16+5MP/13+8MP ISP, MIPI CSI 4/4/2, FD, DRC
> >>>  * Connectivity: USB 2.0 DRD, USI (SPI/UART/I2C), HSI2C, I3C, ADC,
> >>> Audio
> >>>
> >>> This patch adds minimal SoC support. Particular board device tree files
> >>> can include exynos850.dtsi file to get SoC related nodes, and then
> >>> reference those nodes further as needed.
> >>>
> >>> Signed-off-by: Sam Protsenko <semen.protsenko@...aro.org>
> >>> ---
> >>>  .../boot/dts/exynos/exynos850-pinctrl.dtsi    | 782 ++++++++++++++++++
> >>>  arch/arm64/boot/dts/exynos/exynos850-usi.dtsi |  30 +
> >>>  arch/arm64/boot/dts/exynos/exynos850.dtsi     | 245 ++++++
> >>>  3 files changed, 1057 insertions(+)
> >>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> >>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos850-usi.dtsi
> >>>  create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi
> >>>
> >>> diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> >>> b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> >>> new file mode 100644
> >>> index 000000000000..4cf0a22cc6db
> >>
> >> [...]
> >>
> >>> +     gic: interrupt-controller@...00000 {
> >>> +             compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
> >>
> >> One thing for sure, it cannot be both. And given that it is
> >> an A55-based SoC, it isn't either. It is more likely a GIC400.
> >>
> >
> > Yes, it's GIC-400, thanks for pointing that out. Will fix that in v2.
> >
> >>> +             #interrupt-cells = <3>;
> >>> +             #address-cells = <0>;
> >>> +             interrupt-controller;
> >>> +             reg = <0x0 0x12a01000 0x1000>,
> >>> +                   <0x0 0x12a02000 0x1000>,
> >>
> >> This is wrong. It is architecturally set to 8kB.
> >>
> >
> > Nice catch! Actually there is an error (typo?) in SoC's TRM, saying
> > that Virtual Interface Control Register starts at 0x3000 offset (from
> > 0x12a00000), where it obviously should be 0x4000, that's probably
> > where this dts error originates from. Btw, I'm also seeing the same
> > error in exynos7.dtsi.
>
> What's the error exactly? The "Virtual interface control register"
> offset (3rd region) is set properly to 0x4000 on Exynos7. Also one for
> the Exynos5433 looks correct.
>

The issue is that 2nd region's size is 0x1000, but it must be 0x2000.
It's defined by GIC-400 architecture, as I understand. Please look at
[1], table 3-1 has very specific offsets and sizes for each functional
block, and each particular SoC must adhere to that spec. So having
0x1000 for 2nd region can't be correct. And because exynos7.dtsi has
GIC-400 as well, and 0x1000 is specified there for 2nd region size
too, so I presume there is the same mistake there.

Can you please check the TRM for Exynos7 SoC (if you have one in your
possession), and see if there is a typo there? E.g. in case of
Exynos850 TRM I can see that in "Register Map Summary" section the
offset for the first register (GICH_HCR) in "Virtual Interface Control
Register" region is specified as 0x3000, where it should be 0x4000, so
it's probably a typo. But the register description is correct, saying
that: "Address = Base Address + 0x4000".

[1] https://developer.arm.com/documentation/ddi0471/b/programmers-model/gic-400-register-map

> > Though I don't have a TRM for Exynos7 SoCs, so
> > not sure if I should go ahead and fix that too. Anyway, for Exynos850,
> > I'll fix that in v2 series.
>
>
> However while we are at addresses - why are you using address-cells 2?
> It adds everywhere additional 0x0 before actual address.
>

Right. For "cpus" node I'll change the address-cells to 1 in my v2
series. I'll keep address-cells=2 for the root node, but I'm going to
encapsulate some nodes into soc node (as you suggested earlier), where
I'll make address-cells=1. That's pretty much how it's done in
exynos7.dtsi and in exynos5433.dtsi, so I guess that's should be fine
(to get rid of superfluous 0x0 and conform with other Exynos DTs)?

>
> Best regards,
> Krzysztof

Powered by blists - more mailing lists