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Message-ID: <CAE-0n53YRQamHMcb1T0oRkSO0_Shhskzpr4oX60UpiEB8ZY63A@mail.gmail.com>
Date: Wed, 4 Aug 2021 11:56:27 -0700
From: Stephen Boyd <swboyd@...omium.org>
To: Sibi Sankar <sibis@...eaurora.org>, bjorn.andersson@...aro.org,
mka@...omium.org, robh+dt@...nel.org
Cc: viresh.kumar@...aro.org, agross@...nel.org, rjw@...ysocki.net,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
dianders@...omium.org, tdas@...eaurora.org
Subject: Re: [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible
for SM8250/8350
Quoting Sibi Sankar (2021-07-29 11:04:42)
> Re-arranging the register regions to support per core L3 DCVS would lead
> to bindings breakage when using an older dt with a newer kernel. So,
> document the EPSS compatible for SM8250/SM8350 SoCs and use them in the
> CPUFreq-hw driver to prevent such breakages.
>
> Signed-off-by: Sibi Sankar <sibis@...eaurora.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@...omium.org>
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