linux-kernel - RE: [PATCH 2/3] mmc: sdhci-of-arasan: Add intel Thunder Bay SOC support to the arasan eMMC driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <MWHPR11MB17891909766F5295AF34B0578CF69@MWHPR11MB1789.namprd11.prod.outlook.com>
Date:   Mon, 9 Aug 2021 05:16:09 +0000
From:   "A, Rashmi" <rashmi.a@...el.com>
To:     Ulf Hansson <ulf.hansson@...aro.org>
CC:     Michal Simek <michal.simek@...inx.com>,
        linux-mmc <linux-mmc@...r.kernel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Kishon <kishon@...com>, Vinod Koul <vkoul@...nel.org>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        "linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
        Mark Gross <mgross@...ux.intel.com>,
        "kris.pan@...ux.intel.com" <kris.pan@...ux.intel.com>,
        "Zhou, Furong" <furong.zhou@...el.com>,
        "Sangannavar, Mallikarjunappa" 
        <mallikarjunappa.sangannavar@...el.com>,
        "Hunter, Adrian" <adrian.hunter@...el.com>,
        "Vaidya, Mahesh R" <mahesh.r.vaidya@...el.com>,
        "Srikandan, Nandhini" <nandhini.srikandan@...el.com>,
        "Demakkanavar, Kenchappa" <kenchappa.demakkanavar@...el.com>
Subject: RE: [PATCH 2/3] mmc: sdhci-of-arasan: Add intel Thunder Bay SOC
 support to the arasan eMMC driver



> -----Original Message-----
> From: Ulf Hansson <ulf.hansson@...aro.org>
> Sent: Friday, August 6, 2021 6:36 PM
> To: A, Rashmi <rashmi.a@...el.com>
> Cc: linux-drivers-review-request@...ists.intel.com; Michal Simek
> <michal.simek@...inx.com>; linux-mmc <linux-mmc@...r.kernel.org>; Linux
> ARM <linux-arm-kernel@...ts.infradead.org>; Linux Kernel Mailing List <linux-
> kernel@...r.kernel.org>; Kishon <kishon@...com>; Vinod Koul
> <vkoul@...nel.org>; Andy Shevchenko
> <andriy.shevchenko@...ux.intel.com>; linux-phy@...ts.infradead.org; Mark
> Gross <mgross@...ux.intel.com>; kris.pan@...ux.intel.com; Zhou, Furong
> <furong.zhou@...el.com>; Sangannavar, Mallikarjunappa
> <mallikarjunappa.sangannavar@...el.com>; Hunter, Adrian
> <adrian.hunter@...el.com>; Vaidya, Mahesh R
> <mahesh.r.vaidya@...el.com>; Srikandan, Nandhini
> <nandhini.srikandan@...el.com>; Demakkanavar, Kenchappa
> <kenchappa.demakkanavar@...el.com>
> Subject: Re: [PATCH 2/3] mmc: sdhci-of-arasan: Add intel Thunder Bay SOC
> support to the arasan eMMC driver
> 
> On Fri, 30 Jul 2021 at 08:33, <rashmi.a@...el.com> wrote:
> >
> > From: Rashmi A <rashmi.a@...el.com>
> >
> > Intel Thunder Bay SoC eMMC controller is based on Arasan eMMC 5.1 host
> > controller IP
> >
> > Signed-off-by: Rashmi A <rashmi.a@...el.com>
> > Reviewed-by: Adrian Hunter <adrian.hunter@...el.com>
> 
> Rashmi, is it safe to apply this separately from the phy driver/dt changes?
> Then I can queue this via my mmc tree, if you like.
No, the phy driver/dt changes must go together with "mmc: sdhci-of-arasan: Add intel Thunder Bay SOC support to the arasan eMMC driver" patch.

Regards
Rashmi
> 
> Kind regards
> Uffe
> 
> > ---
> >  drivers/mmc/host/sdhci-of-arasan.c | 29
> ++++++++++++++++++++++++++++-
> >  1 file changed, 28 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/host/sdhci-of-arasan.c
> > b/drivers/mmc/host/sdhci-of-arasan.c
> > index 839965f7c717..6f202fb7a546 100644
> > --- a/drivers/mmc/host/sdhci-of-arasan.c
> > +++ b/drivers/mmc/host/sdhci-of-arasan.c
> > @@ -185,6 +185,13 @@ static const struct sdhci_arasan_soc_ctl_map
> intel_lgm_sdxc_soc_ctl_map = {
> >         .hiword_update = false,
> >  };
> >
> > +static const struct sdhci_arasan_soc_ctl_map thunderbay_soc_ctl_map = {
> > +       .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
> > +       .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
> > +       .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
> > +       .hiword_update = false,
> > +};
> > +
> >  static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map
> = {
> >         .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
> >         .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 }, @@
> > -430,6 +437,15 @@ static const struct sdhci_pltfm_data
> sdhci_arasan_cqe_pdata = {
> >                         SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
> >  };
> >
> > +static const struct sdhci_pltfm_data sdhci_arasan_thunderbay_pdata = {
> > +       .ops = &sdhci_arasan_cqe_ops,
> > +       .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
> SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
> > +       .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> > +               SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
> > +               SDHCI_QUIRK2_STOP_WITH_TC |
> > +               SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
> > +};
> > +
> >  #ifdef CONFIG_PM_SLEEP
> >  /**
> >   * sdhci_arasan_suspend - Suspend method for the driver @@ -1098,6
> > +1114,12 @@ static struct sdhci_arasan_of_data
> sdhci_arasan_generic_data = {
> >         .clk_ops = &arasan_clk_ops,
> >  };
> >
> > +static const struct sdhci_arasan_of_data sdhci_arasan_thunderbay_data =
> {
> > +       .soc_ctl_map = &thunderbay_soc_ctl_map,
> > +       .pdata = &sdhci_arasan_thunderbay_pdata,
> > +       .clk_ops = &arasan_clk_ops,
> > +};
> > +
> >  static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
> >         .ops = &sdhci_arasan_cqe_ops,
> >         .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | @@ -1231,6
> > +1253,10 @@ static const struct of_device_id sdhci_arasan_of_match[] = {
> >                 .compatible = "intel,keembay-sdhci-5.1-sdio",
> >                 .data = &intel_keembay_sdio_data,
> >         },
> > +       {
> > +               .compatible = "intel,thunderbay-sdhci-5.1",
> > +               .data = &sdhci_arasan_thunderbay_data,
> > +       },
> >         /* Generic compatible below here */
> >         {
> >                 .compatible = "arasan,sdhci-8.9a", @@ -1582,7 +1608,8
> > @@ static int sdhci_arasan_probe(struct platform_device *pdev)
> >
> >         if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
> >             of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
> > -           of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
> > +           of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio") ||
> > +           of_device_is_compatible(np, "intel,thunderbay-sdhci-5.1"))
> > + {
> >                 sdhci_arasan_update_clockmultiplier(host, 0x0);
> >                 sdhci_arasan_update_support64b(host, 0x0);
> >
> > --
> > 2.17.1
> >