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Message-ID: <CAOQ_QshJmjSUGVVLOqGJFicDpGfvf159W8utDWMpuT6i4fCBQQ@mail.gmail.com>
Date: Mon, 9 Aug 2021 09:12:52 -0700
From: Oliver Upton <oupton@...gle.com>
To: Marc Zyngier <maz@...nel.org>
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Mark Rutland <mark.rutland@....com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Peter Shier <pshier@...gle.com>,
Raghavendra Rao Ananta <rananta@...gle.com>,
Ricardo Koller <ricarkol@...gle.com>,
Will Deacon <will@...nel.org>,
Catalin Marinas <catalin.marinas@....com>,
Linus Walleij <linus.walleij@...aro.org>,
kernel-team@...roid.com
Subject: Re: [PATCH 02/13] clocksource/arm_arch_timer: Extend write side of
timer register accessors to u64
On Mon, Aug 9, 2021 at 8:27 AM Marc Zyngier <maz@...nel.org> wrote:
>
> The various accessors for the timer sysreg and MMIO registers are
> currently hardwired to 32bit. However, we are about to introduce
> the use of the CVAL registers, which require a 64bit access.
>
> Upgrade the write side of the accessors to take a 64bit value
> (the read side is left untouched as we don't plan to ever read
> back any of these registers).
>
> No functional change expected.
>
> Signed-off-by: Marc Zyngier <maz@...nel.org>
Reviewed-by: Oliver Upton <oupton@...gle.com>
> ---
> arch/arm/include/asm/arch_timer.h | 10 +++++-----
> arch/arm64/include/asm/arch_timer.h | 2 +-
> drivers/clocksource/arm_arch_timer.c | 10 +++++-----
> 3 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
> index 0c09afaa590d..88075c7f4bfd 100644
> --- a/arch/arm/include/asm/arch_timer.h
> +++ b/arch/arm/include/asm/arch_timer.h
> @@ -24,24 +24,24 @@ int arch_timer_arch_init(void);
> * the code. At least it does so with a recent GCC (4.6.3).
> */
> static __always_inline
> -void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
> +void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
> {
> if (access == ARCH_TIMER_PHYS_ACCESS) {
> switch (reg) {
> case ARCH_TIMER_REG_CTRL:
> - asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
> + asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" ((u32)val));
> break;
> case ARCH_TIMER_REG_TVAL:
> - asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
> + asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" ((u32)val));
> break;
> }
> } else if (access == ARCH_TIMER_VIRT_ACCESS) {
> switch (reg) {
> case ARCH_TIMER_REG_CTRL:
> - asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val));
> + asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" ((u32)val));
> break;
> case ARCH_TIMER_REG_TVAL:
> - asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val));
> + asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" ((u32)val));
> break;
> }
> }
> diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
> index 8e3b2ac60c30..107afb721749 100644
> --- a/arch/arm64/include/asm/arch_timer.h
> +++ b/arch/arm64/include/asm/arch_timer.h
> @@ -89,7 +89,7 @@ static inline notrace u64 arch_timer_read_cntvct_el0(void)
> * the code.
> */
> static __always_inline
> -void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
> +void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
> {
> if (access == ARCH_TIMER_PHYS_ACCESS) {
> switch (reg) {
> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index 9db5c16e31e7..0b2bac3ef7ce 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -100,27 +100,27 @@ early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
> */
>
> static __always_inline
> -void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
> +void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,
> struct clock_event_device *clk)
> {
> if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
> struct arch_timer *timer = to_arch_timer(clk);
> switch (reg) {
> case ARCH_TIMER_REG_CTRL:
> - writel_relaxed(val, timer->base + CNTP_CTL);
> + writel_relaxed((u32)val, timer->base + CNTP_CTL);
> break;
> case ARCH_TIMER_REG_TVAL:
> - writel_relaxed(val, timer->base + CNTP_TVAL);
> + writel_relaxed((u32)val, timer->base + CNTP_TVAL);
> break;
> }
> } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
> struct arch_timer *timer = to_arch_timer(clk);
> switch (reg) {
> case ARCH_TIMER_REG_CTRL:
> - writel_relaxed(val, timer->base + CNTV_CTL);
> + writel_relaxed((u32)val, timer->base + CNTV_CTL);
> break;
> case ARCH_TIMER_REG_TVAL:
> - writel_relaxed(val, timer->base + CNTV_TVAL);
> + writel_relaxed((u32)val, timer->base + CNTV_TVAL);
> break;
> }
> } else {
> --
> 2.30.2
>
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