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Message-ID: <20210811084648.66ddff29@coco.lan>
Date: Wed, 11 Aug 2021 08:46:48 +0200
From: Mauro Carvalho Chehab <mchehab+huawei@...nel.org>
To: Rob Herring <robh@...nel.org>
Cc: Linuxarm <linuxarm@...wei.com>, mauro.chehab@...wei.com,
Binghui Wang <wangbinghui@...ilicon.com>,
Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
Jingoo Han <jingoohan1@...il.com>,
Xiaowei Song <songxiaowei@...ilicon.com>,
devicetree@...r.kernel.org,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
PCI <linux-pci@...r.kernel.org>, linux-phy@...ts.infradead.org
Subject: Re: [PATCH v3 0/4] DT schema changes for HiKey970 PCIe hardware to
work
Em Tue, 10 Aug 2021 11:13:48 -0600
Rob Herring <robh@...nel.org> escreveu:
> > > > compatible = "pciclass,0604";
> > > > device_type = "pci";
> > > > #address-cells = <3>;
> > > > #size-cells = <2>;
> > > > ranges;
> > > > };
> > > > pcie@1,0 { // Lane 4: M.2
> > >
> > > These 3 nodes (1, 5, 7) need to be child nodes of the above node.
>
> This was the main issue.
Ok, placing 1, 5, 7 as child nodes of 0 worked, with the attached
DT schema:
$ ls -l $(find /sys/devices/platform/soc/f4000000.pcie/ -name of_node)
lrwxrwxrwx 1 root root 0 ago 11 08:43 /sys/devices/platform/soc/f4000000.pcie/of_node -> ../../../../firmware/devicetree/base/soc/pcie@...00000
lrwxrwxrwx 1 root root 0 ago 11 08:43 /sys/devices/platform/soc/f4000000.pcie/pci0000:00/0000:00:00.0/0000:01:00.0/0000:02:01.0/of_node -> ../../../../../../../../firmware/devicetree/base/soc/pcie@...00000/pcie@0,0/pcie@0,0/pcie@1,0
lrwxrwxrwx 1 root root 0 ago 11 08:43 /sys/devices/platform/soc/f4000000.pcie/pci0000:00/0000:00:00.0/0000:01:00.0/0000:02:01.0/pci_bus/0000:03/of_node -> ../../../../../../../../../../firmware/devicetree/base/soc/pcie@...00000/pcie@0,0/pcie@0,0/pcie@1,0
lrwxrwxrwx 1 root root 0 ago 11 08:43 /sys/devices/platform/soc/f4000000.pcie/pci0000:00/0000:00:00.0/0000:01:00.0/0000:02:05.0/of_node -> ../../../../../../../../firmware/devicetree/base/soc/pcie@...00000/pcie@0,0/pcie@0,0/pcie@5,0
lrwxrwxrwx 1 root root 0 ago 11 08:43 /sys/devices/platform/soc/f4000000.pcie/pci0000:00/0000:00:00.0/0000:01:00.0/0000:02:05.0/pci_bus/0000:05/of_node -> ../../../../../../../../../../firmware/devicetree/base/soc/pcie@...00000/pcie@0,0/pcie@0,0/pcie@5,0
lrwxrwxrwx 1 root root 0 ago 11 08:43 /sys/devices/platform/soc/f4000000.pcie/pci0000:00/0000:00:00.0/0000:01:00.0/0000:02:07.0/of_node -> ../../../../../../../../firmware/devicetree/base/soc/pcie@...00000/pcie@0,0/pcie@0,0/pcie@7,0
lrwxrwxrwx 1 root root 0 ago 11 08:43 /sys/devices/platform/soc/f4000000.pcie/pci0000:00/0000:00:00.0/0000:01:00.0/0000:02:07.0/pci_bus/0000:06/of_node -> ../../../../../../../../../../firmware/devicetree/base/soc/pcie@...00000/pcie@0,0/pcie@0,0/pcie@7,0
lrwxrwxrwx 1 root root 0 ago 11 08:43 /sys/devices/platform/soc/f4000000.pcie/pci0000:00/0000:00:00.0/0000:01:00.0/of_node -> ../../../../../../../firmware/devicetree/base/soc/pcie@...00000/pcie@0,0/pcie@0,0
lrwxrwxrwx 1 root root 0 ago 11 08:43 /sys/devices/platform/soc/f4000000.pcie/pci0000:00/0000:00:00.0/0000:01:00.0/pci_bus/0000:02/of_node -> ../../../../../../../../../firmware/devicetree/base/soc/pcie@...00000/pcie@0,0/pcie@0,0
lrwxrwxrwx 1 root root 0 ago 11 08:43 /sys/devices/platform/soc/f4000000.pcie/pci0000:00/0000:00:00.0/of_node -> ../../../../../../firmware/devicetree/base/soc/pcie@...00000/pcie@0,0
lrwxrwxrwx 1 root root 0 ago 11 08:43 /sys/devices/platform/soc/f4000000.pcie/pci0000:00/0000:00:00.0/pci_bus/0000:01/of_node -> ../../../../../../../../firmware/devicetree/base/soc/pcie@...00000/pcie@0,0
lrwxrwxrwx 1 root root 0 ago 11 08:43 /sys/devices/platform/soc/f4000000.pcie/pci0000:00/pci_bus/0000:00/of_node -> ../../../../../../../firmware/devicetree/base/soc/pcie@...00000
The logs also seem OK on my eyes:
[ 3.911082] (null): pci_set_bus_of_node: of_node: /soc/pcie@...00000
[ 4.001104] pci 0000:00:00.0: pci_set_of_node: of_node: /soc/pcie@...00000
[ 4.043609] pci_bus 0000:01: pci_set_bus_of_node: of_node: /soc/pcie@...00000/pcie@0,0
[ 4.076756] pci 0000:01:00.0: pci_set_of_node: of_node: /soc/pcie@...00000/pcie@0,0
[ 4.120652] pci_bus 0000:02: pci_set_bus_of_node: of_node: /soc/pcie@...00000/pcie@0,0/pcie@0,0
[ 4.150766] pci 0000:02:01.0: pci_set_of_node: of_node: /soc/pcie@...00000/pcie@0,0/pcie@0,0
[ 4.196413] pci 0000:02:04.0: pci_set_of_node: of_node: /soc/pcie@...00000/pcie@0,0/pcie@0,0
[ 4.238896] pci 0000:02:05.0: pci_set_of_node: of_node: /soc/pcie@...00000/pcie@0,0/pcie@0,0
[ 4.280116] pci 0000:02:07.0: pci_set_of_node: of_node: /soc/pcie@...00000/pcie@0,0/pcie@0,0
[ 4.309821] pci 0000:02:09.0: pci_set_of_node: of_node: /soc/pcie@...00000/pcie@0,0/pcie@0,0
[ 4.370830] pci_bus 0000:03: pci_set_bus_of_node: of_node: /soc/pcie@...00000/pcie@0,0/pcie@0,0/pcie@1,0
[ 4.382345] pci_bus 0000:04: pci_set_bus_of_node: of_node: (null)
[ 4.411966] pci_bus 0000:05: pci_set_bus_of_node: of_node: /soc/pcie@...00000/pcie@0,0/pcie@0,0/pcie@5,0
[ 4.439898] pci_bus 0000:06: pci_set_bus_of_node: of_node: /soc/pcie@...00000/pcie@0,0/pcie@0,0/pcie@7,0
[ 4.491616] pci 0000:06:00.0: pci_set_of_node: of_node: /soc/pcie@...00000/pcie@0,0/pcie@0,0/pcie@7,0
[ 4.519907] pci_bus 0000:07: pci_set_bus_of_node: of_node: (null)
Thanks,
Mauro
pcie@...00000 {
compatible = "hisilicon,kirin970-pcie";
reg = <0x0 0xf4000000 0x0 0x1000000>,
<0x0 0xfc180000 0x0 0x1000>,
<0x0 0xf5000000 0x0 0x2000>;
reg-names = "dbi", "apb", "config";
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
phys = <&pcie_phy>;
ranges = <0x02000000 0x0 0x00000000
0x0 0xf6000000
0x0 0x02000000>;
num-lanes = <1>;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0x0 0 0 1
&gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<0x0 0 0 2
&gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<0x0 0 0 3
&gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<0x0 0 0 4
&gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&gpio7 0 0>;
hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>,
<&gpio20 6 0>;
pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
reg = <0x80 0 0 0 0>;
compatible = "pciclass,0604";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
bus-range = <0x01 0xff>;
msi-parent = <&its_pcie>;
pcie@0,0 { // Lane 0: upstream
reg = <0x010000 0 0 0 0>;
compatible = "pciclass,0604";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@1,0 { // Lane 4: M.2
reg = <0x010800 0 0 0 0>;
compatible = "pciclass,0604";
device_type = "pci";
reset-gpios = <&gpio3 1 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
pcie@5,0 { // Lane 5: Mini PCIe
reg = <0x012800 0 0 0 0>;
compatible = "pciclass,0604";
device_type = "pci";
reset-gpios = <&gpio27 4 0 >;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
pcie@7,0 { // Lane 6: Ethernet
reg = <0x013800 0 0 0 0>;
compatible = "pciclass,0604";
device_type = "pci";
reset-gpios = <&gpio25 2 0 >;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
};
};
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