linux-kernel - RE: [PATCH net-next 1/1] net: phy: marvell10g: Add WAKE

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <PH0PR11MB4950EAF1FC749EAAE3FDFCB7D8FD9@PH0PR11MB4950.namprd11.prod.outlook.com>
Date:   Mon, 16 Aug 2021 03:19:34 +0000
From:   "Song, Yoong Siang" <yoong.siang.song@...el.com>
To:     Andrew Lunn <andrew@...n.ch>,
        "Russell King (Oracle)" <linux@...linux.org.uk>
CC:     Marek Behún <kabel@...nel.org>,
        Heiner Kallweit <hkallweit1@...il.com>,
        "David S . Miller" <davem@...emloft.net>,
        "Jakub Kicinski" <kuba@...nel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH net-next 1/1] net: phy: marvell10g: Add WAKE_PHY support
 to WOL event

> > How does this work if the driver has no interrupt support? What is the
> > hardware setup this has been tested with?
> 
> Hi Russell
> 
> We already know from previous patches that the Intel hardware is broken,
> and does not actually deliver the interrupt which caused the wake up. So i
> assume this just continues on with the same broken hardware, but they have
> a different PHY connected.

Hi Russell & Andrew,

This is tested on Intel Elkhart Lake (EHL) board. We are using polling mode.
Both WoL interrupt and link change interrupt are the same pin which is
routed to PMC. PMC will wake up the system when there is WoL event.

Regards
Siang

> 
> > What if we later want to add interrupt support to this driver to
> > support detecting changes in link state - isn't using this bit in the
> > interrupt enable register going to confict with that?
> 
> Agreed. If the interrupt register is being used, i think we need this patchset to
> add proper interrupt support. Can you recommend a board they can buy off
> the shelf with the interrupt wired up? Or maybe Intel can find a hardware
> engineer to add a patch wire to link the interrupt output to a SoC pin that can
> do interrupts.
> 
> 	  Andrew