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Date:   Mon, 23 Aug 2021 06:02:08 +0000
From:   "Sanil, Shruthi" <shruthi.sanil@...el.com>
To:     Rob Herring <robh@...nel.org>,
        Andy Shevchenko <andy.shevchenko@...il.com>
CC:     "daniel.lezcano@...aro.org" <daniel.lezcano@...aro.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "andriy.shevchenko@...ux.intel.com" 
        <andriy.shevchenko@...ux.intel.com>,
        "kris.pan@...ux.intel.com" <kris.pan@...ux.intel.com>,
        "mgross@...ux.intel.com" <mgross@...ux.intel.com>,
        "Thokala, Srikanth" <srikanth.thokala@...el.com>,
        "Raja Subramanian, Lakshmi Bai" 
        <lakshmi.bai.raja.subramanian@...el.com>,
        "Sangannavar, Mallikarjunappa" 
        <mallikarjunappa.sangannavar@...el.com>
Subject: RE: [PATCH v5 1/2] dt-bindings: timer: Add bindings for Intel Keem
 Bay SoC Timer

> -----Original Message-----
> From: Sanil, Shruthi
> Sent: Thursday, August 12, 2021 10:19 PM
> To: Andy Shevchenko <andy.shevchenko@...il.com>
> Cc: Rob Herring <robh@...nel.org>; daniel.lezcano@...aro.org;
> tglx@...utronix.de; linux-kernel@...r.kernel.org;
> devicetree@...r.kernel.org; andriy.shevchenko@...ux.intel.com;
> kris.pan@...ux.intel.com; mgross@...ux.intel.com; Thokala, Srikanth
> <Srikanth.Thokala@...el.com>; Raja Subramanian, Lakshmi Bai
> <lakshmi.bai.raja.subramanian@...el.com>; Sangannavar, Mallikarjunappa
> <mallikarjunappa.sangannavar@...el.com>
> Subject: RE: [PATCH v5 1/2] dt-bindings: timer: Add bindings for Intel Keem
> Bay SoC Timer
> 
> > -----Original Message-----
> > From: Andy Shevchenko <andy.shevchenko@...il.com>
> > Sent: Wednesday, August 4, 2021 1:08 PM
> > To: Sanil, Shruthi <shruthi.sanil@...el.com>
> > Cc: Rob Herring <robh@...nel.org>; daniel.lezcano@...aro.org;
> > tglx@...utronix.de; linux-kernel@...r.kernel.org;
> > devicetree@...r.kernel.org; andriy.shevchenko@...ux.intel.com;
> > kris.pan@...ux.intel.com; mgross@...ux.intel.com; Thokala, Srikanth
> > <srikanth.thokala@...el.com>; Raja Subramanian, Lakshmi Bai
> > <lakshmi.bai.raja.subramanian@...el.com>; Sangannavar, Mallikarjunappa
> > <mallikarjunappa.sangannavar@...el.com>
> > Subject: Re: [PATCH v5 1/2] dt-bindings: timer: Add bindings for Intel
> > Keem Bay SoC Timer
> >
> > On Wed, Aug 4, 2021 at 8:35 AM Sanil, Shruthi
> > <shruthi.sanil@...el.com>
> > wrote:
> > > > From: Rob Herring <robh@...nel.org>
> > > > Sent: Tuesday, August 3, 2021 4:14 AM
> >
> > ...
> >
> > > > > +properties:
> > > >
> > > > You need a 'compatible' here. Otherwise, how does one know what
> 'reg'
> > > > contains. Also, without it, this schema will never be applied.
> > > >
> > >
> > > This is a parent block that has the common configuration register
> > > address
> > defined which we would need during the initialization of the child
> > nodes. This block in itself is not doing anything. We have this
> > because, we have a common register that is required to be accessed
> > during all the timers and counter initialization.
> > > The child nodes have the compatible string, which is used in the
> > > driver. I
> > have validated this on the Keem Bay HW and see that the timer probes
> > are being called and the timers are functional as expected.
> >
> > I think I understand now. The problem is that the current state of
> > affairs with this block is incorrect software representation. What you
> > need is to create an MFD device driver (for which the compatible will
> > exactly the one Rob is telling
> > about) and from it you register the rest of your drivers. The existing
> > drivers for this block should be converted to MFD schema.
> 
> Sure Andy, I shall check on this and get back.
> Thank You!
> 

Hi Rob,
Do you agree with the above proposal of creating a MFD device with compatible string "simple-mfd"? 

> >
> > --
> > With Best Regards,
> > Andy Shevchenko

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