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Message-Id: <1630339489-23172-1-git-send-email-khsieh@codeaurora.org>
Date: Mon, 30 Aug 2021 09:04:49 -0700
From: Kuogee Hsieh <khsieh@...eaurora.org>
To: robdclark@...il.com, sean@...rly.run, swboyd@...omium.org,
vkoul@...nel.org, agross@...nel.org, bjorn.andersson@...aro.org,
robh+dt@...nel.org, devicetree@...r.kernel.org
Cc: abhinavk@...eaurora.org, aravindh@...eaurora.org,
khsieh@...eaurora.org, mkrishn@...eaurora.org,
kalyan_t@...eaurora.org, rajeevny@...eaurora.org,
freedreno@...ts.freedesktop.org, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v2] arm64: dts: qcom: sc7280: Add Display Port node
Changes in v2:
-- break this patch into 3 patches
Signed-off-by: Kuogee Hsieh <khsieh@...eaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 88 +++++++++++++++++++++++++++++++++++-
1 file changed, 87 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index c29226b..f224029 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3202,6 +3202,13 @@
remote-endpoint = <&edp_in>;
};
};
+
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&dp_in>;
+ };
+ };
};
mdp_opp_table: mdp-opp-table {
@@ -3389,6 +3396,78 @@
};
};
};
+
+ msm_dp: displayport-controller@...0000 {
+ status = "disabled";
+ compatible = "qcom,sc7180-dp", "qcom,sc7280-dp";
+
+ reg = <0 0x0ae90000 0 0x1400>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+ #clock-cells = <1>;
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
+ phys = <&dp_phy>;
+ phy-names = "dp";
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SC7280_CX>;
+
+ #sound-dai-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dp_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dp_out: endpoint { };
+ };
+ };
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
};
dispcc: clock-controller@...0000 {
@@ -3398,7 +3477,8 @@
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&dsi_phy 0>,
<&dsi_phy 1>,
- <0>, <0>,
+ <&dp_phy 0>,
+ <&dp_phy 1>,
<&msm_edp 0>,
<&msm_edp 1>;
clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
@@ -3525,6 +3605,12 @@
};
};
+ dp_hot_plug_det: dp-hot-plug-det {
+ pins = "gpio47";
+ function = "dp_hot";
+ bias-disable;
+ };
+
qspi_clk: qspi-clk {
pins = "gpio14";
function = "qspi_clk";
--
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