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Message-ID: <20210902092954.28359-1-kavyasree.kotagiri@microchip.com>
Date: Thu, 2 Sep 2021 14:59:54 +0530
From: <kavyasree.kotagiri@...rochip.com>
To: <robh+dt@...nel.org>, <mturquette@...libre.com>, <sboyd@...nel.org>
CC: <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-clk@...r.kernel.org>, <UNGLinuxDriver@...rochip.com>,
<Eugen.Hristev@...rochip.com>, <Kavyasree.Kotagiri@...rochip.com>,
<Manohar.Puri@...rochip.com>
Subject: [PATCH 3/3] dt-bindings: clock: lan966x: Add LAN966X Clock Controller
From: Kavyasree Kotagiri <Kavyasree.Kotagiri@...rochip.com>
This adds the DT bindings documentation for lan966x SoC
generic clock controller.
Signed-off-by: Kavya Sree Kotagiri <kavyasree.kotagiri@...rochip.com>
---
.../bindings/clock/microchip,lan966x-gck.yaml | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
diff --git a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
new file mode 100644
index 000000000000..0df765f628c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip LAN966X Generic Clock Controller
+
+maintainers:
+ - Kavya Sree Kotagiri <kavyasree.kotagiri@...rochip.com>
+
+description: |
+ The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
+ ddr_clk and sys_clk. This clock controller generates and supplies
+ clock to various peripherals within the SoC.
+
+properties:
+ compatible:
+ const: microchip,lan966x-gck
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clks: clock-controller@...c00a8 {
+ compatible = "microchip,lan966x-gck";
+ #clock-cells = <1>;
+ clocks = <&cpu_clk>;
+ reg = <0xe00c00a8 0x38>;
+ };
+...
--
2.17.1
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