linux-kernel - Re: [PATCH 3/3] dt-bindings: clock: lan966x: Add LAN966X Clock Controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Tue, 7 Sep 2021 14:00:15 -0500
From:   Rob Herring <robh@...nel.org>
To:     kavyasree.kotagiri@...rochip.com
Cc:     mturquette@...libre.com, sboyd@...nel.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-clk@...r.kernel.org, UNGLinuxDriver@...rochip.com,
        Eugen.Hristev@...rochip.com, Manohar.Puri@...rochip.com
Subject: Re: [PATCH 3/3] dt-bindings: clock: lan966x: Add LAN966X Clock
 Controller

On Thu, Sep 02, 2021 at 02:59:54PM +0530, kavyasree.kotagiri@...rochip.com wrote:
> From: Kavyasree Kotagiri <Kavyasree.Kotagiri@...rochip.com>

Ah, here's the rest. The threading of your series is broken.

> 
> This adds the DT bindings documentation for lan966x SoC
> generic clock controller.
> 
> Signed-off-by: Kavya Sree Kotagiri <kavyasree.kotagiri@...rochip.com>

Please make your author and Sob name and email match.

> ---
>  .../bindings/clock/microchip,lan966x-gck.yaml | 46 +++++++++++++++++++
>  1 file changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
> new file mode 100644
> index 000000000000..0df765f628c4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip LAN966X Generic Clock Controller
> +
> +maintainers:
> +  - Kavya Sree Kotagiri <kavyasree.kotagiri@...rochip.com>
> +
> +description: |
> +  The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
> +  ddr_clk and sys_clk. This clock controller generates and supplies
> +  clock to various peripherals within the SoC.
> +
> +properties:
> +  compatible:
> +    const: microchip,lan966x-gck
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    clks: clock-controller@...c00a8 {
> +        compatible = "microchip,lan966x-gck";
> +        #clock-cells = <1>;
> +        clocks = <&cpu_clk>;
> +        reg = <0xe00c00a8 0x38>;

Looks like this is part of some other block?

> +    };
> +...
> --
> 2.17.1
> 
>