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Message-Id: <20210906183621.21075-2-shruthi.sanil@intel.com>
Date: Tue, 7 Sep 2021 00:06:20 +0530
From: shruthi.sanil@...el.com
To: daniel.lezcano@...aro.org, tglx@...utronix.de, robh+dt@...nel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Cc: andriy.shevchenko@...ux.intel.com, kris.pan@...ux.intel.com,
mgross@...ux.intel.com, srikanth.thokala@...el.com,
lakshmi.bai.raja.subramanian@...el.com,
mallikarjunappa.sangannavar@...el.com, shruthi.sanil@...el.com
Subject: [PATCH v6 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer
From: Shruthi Sanil <shruthi.sanil@...el.com>
Add Device Tree bindings for the Timer IP, which can be used as
clocksource and clockevent device in the Intel Keem Bay SoC.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@...el.com>
Signed-off-by: Shruthi Sanil <shruthi.sanil@...el.com>
---
.../bindings/timer/intel,keembay-timer.yaml | 173 ++++++++++++++++++
1 file changed, 173 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
new file mode 100644
index 000000000000..f40b23e47e75
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Keem Bay SoC Timers
+
+maintainers:
+ - Shruthi Sanil <shruthi.sanil@...el.com>
+
+description: |
+ The Intel Keem Bay timer driver supports 1 free running counter and 8 timers.
+ Each timer is capable of generating inividual interrupt.
+ Both the features are enabled through the timer general config register.
+
+ The parent node represents the common general configuration details and
+ the child nodes represents the counter and timers.
+
+properties:
+ compatible:
+ enum:
+ - simple-mfd
+ - intel, keembay-gpt-creg
+
+ reg:
+ description: General configuration register address and length.
+ maxItems: 1
+
+ ranges: true
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - ranges
+ - "#address-cells"
+ - "#size-cells"
+
+patternProperties:
+ "^counter@[0-9a-f]+$":
+ type: object
+ description: Properties for Intel Keem Bay counter
+
+ properties:
+ compatible:
+ enum:
+ - intel,keembay-counter
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - clocks
+
+ "^timer@[0-9a-f]+$":
+ type: object
+ description: Properties for Intel Keem Bay timer
+
+ properties:
+ compatible:
+ enum:
+ - intel,keembay-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #define KEEM_BAY_A53_TIM
+
+ soc {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ gpt@...31000 {
+ compatible = "intel,keembay-gpt-creg", "simple-mfd";
+ reg = <0x0 0x20331000 0x0 0xc>;
+ ranges = <0x0 0x0 0x20330000 0xF0>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ counter@e8 {
+ compatible = "intel,keembay-counter";
+ reg = <0xe8 0x8>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@10 {
+ compatible = "intel,keembay-timer";
+ reg = <0x10 0xc>;
+ interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@20 {
+ compatible = "intel,keembay-timer";
+ reg = <0x20 0xc>;
+ interrupts = <GIC_SPI 0x4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@30 {
+ compatible = "intel,keembay-timer";
+ reg = <0x30 0xc>;
+ interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@40 {
+ compatible = "intel,keembay-timer";
+ reg = <0x40 0xc>;
+ interrupts = <GIC_SPI 0x6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@50 {
+ compatible = "intel,keembay-timer";
+ reg = <0x50 0xc>;
+ interrupts = <GIC_SPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@60 {
+ compatible = "intel,keembay-timer";
+ reg = <0x60 0xc>;
+ interrupts = <GIC_SPI 0x8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@70 {
+ compatible = "intel,keembay-timer";
+ reg = <0x70 0xc>;
+ interrupts = <GIC_SPI 0x9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@80 {
+ compatible = "intel,keembay-timer";
+ reg = <0x80 0xc>;
+ interrupts = <GIC_SPI 0xa IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+ };
+ };
+
+...
--
2.17.1
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