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Message-Id: <20210907083723.7725-5-granquet@baylibre.com>
Date: Tue, 7 Sep 2021 10:37:21 +0200
From: Guillaume Ranquet <granquet@...libre.com>
To: unlisted-recipients:; (no To-header on input)
Cc: Chun-Kuang Hu <chunkuang.hu@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Chunfeng Yun <chunfeng.yun@...iatek.com>,
Kishon Vijay Abraham I <kishon@...com>,
Vinod Koul <vkoul@...nel.org>, CK Hu <ck.hu@...iatek.com>,
Jitao shi <jitao.shi@...iatek.com>,
dri-devel@...ts.freedesktop.org,
linux-mediatek@...ts.infradead.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org
Subject: [PATCH 4/4] dt-bindings: display: mediatek: add MT8195 hdmi bindings
Add Mediatek HDMI and HDMI-DDC bindings for MT8195 SoC.
Signed-off-by: Guillaume Ranquet <granquet@...libre.com>
---
.../mediatek/mediatek,mt8195-hdmi-ddc.yaml | 46 +++++++++
.../mediatek/mediatek,mt8195-hdmi.yaml | 99 +++++++++++++++++++
2 files changed, 145 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
new file mode 100644
index 000000000000..ae3cc0ae457f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek HDMI DDC Device Tree Bindings for mt8195
+
+maintainers:
+ - CK Hu <ck.hu@...iatek.com>
+ - Jitao shi <jitao.shi@...iatek.com>
+
+description: |
+ The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-hdmi-ddc
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: ddc-i2c
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ hdmiddc0: ddc_i2c {
+ compatible = "mediatek,mt8195-hdmi-ddc";
+ clocks = <&clk26m>;
+ clock-names = "ddc-i2c";
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
new file mode 100644
index 000000000000..b5d5f7f79c71
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek HDMI Encoder Device Tree Bindings for mt8195
+
+maintainers:
+ - CK Hu <ck.hu@...iatek.com>
+ - Jitao shi <jitao.shi@...iatek.com>
+
+description: |
+ The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
+ its parallel input.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-hdmi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PLL divider
+ - description: PLL divider
+ - description: HDCP engine clock
+ - description: PLL divider
+ - description: HDCP engine clock
+ - description: Bus clock
+ - description: HDMI clock for vpp_split module
+
+ clock-names:
+ items:
+ - const: univpll_d6_d4
+ - const: msdcpll_d2
+ - const: hdmi_apb_sel
+ - const: univpll_d4_d8
+ - const: hdcp_sel
+ - const: hdcp24_sel
+ - const: split_hdmi
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: hdmi
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ hdmi0: hdmi@...00000 {
+ compatible = "mediatek,mt8195-hdmi";
+ reg = <0 0x1c300000 0 0x1000>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D4>,
+ <&topckgen CLK_TOP_MSDCPLL_D2>,
+ <&topckgen CLK_TOP_HDMI_APB>,
+ <&topckgen CLK_TOP_UNIVPLL_D4_D8>,
+ <&topckgen CLK_TOP_HDCP>,
+ <&topckgen CLK_TOP_HDCP_24M>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
+ clock-names = "univpll_d6_d4",
+ "msdcpll_d2",
+ "hdmi_apb_sel",
+ "univpll_d4_d8",
+ "hdcp_sel",
+ "hdcp24_sel",
+ "split_hdmi";
+ interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ cec = <&cec>;
+ ddc-i2c-bus = <&hdmiddc0>;
+ status = "disabled";
+ };
+
+...
--
2.31.1
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