linux-kernel - Re: [PATCH 10/10] arm64: errata: Add workaround for TSB flush failures

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Message-ID: <37b9e52a-9790-2d9d-f613-b95b7aa50994@arm.com>
Date:   Wed, 8 Sep 2021 14:39:28 +0100
From:   Suzuki K Poulose <suzuki.poulose@....com>
To:     Anshuman Khandual <anshuman.khandual@....com>,
        Marc Zyngier <maz@...nel.org>
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        coresight@...ts.linaro.org, will@...nel.org,
        catalin.marinas@....com, james.morse@....com,
        mathieu.poirier@...aro.org, mike.leach@...aro.org,
        leo.yan@...aro.org, mark.rutland@....com
Subject: Re: [PATCH 10/10] arm64: errata: Add workaround for TSB flush
 failures

On 03/08/2021 04:51, Anshuman Khandual wrote:
> 
> 
> On 8/2/21 3:05 PM, Marc Zyngier wrote:
>> On 2021-08-02 10:12, Anshuman Khandual wrote:
>>> On 7/29/21 4:11 PM, Suzuki K Poulose wrote:
>>>> On 29/07/2021 10:55, Marc Zyngier wrote:
>>>>> On Wed, 28 Jul 2021 14:52:17 +0100,
>>>>> Suzuki K Poulose <suzuki.poulose@....com>
>>
>> [...]
>>
>>>>>> +            __tsb_csync();                        \
>>>>>> +            __tsb_csync();                        \
>>>>>> +        } else {                            \
>>>>>> +            __tsb_csync();                        \
>>>>>> +        }                                \
>>>>>
>>>>> nit: You could keep one unconditional __tsb_csync().
>>>>
>>>> I thought about that, I was worried if the CPU expects them back to back
>>>> without any other instructions in between them. Thinking about it a bit
>>>> more, it doesn't look like that is the case. I will confirm this and
>>>> change it accordingly.
>>> But its a very subtle change which might be difficult to debug and blame
>>> later on, if indeed both the instructions need to be back to back. Seems
>>> like just better to leave this unchanged.
>>
>> Is that an actual requirement? Sounds like you want to find out
>> from the errata document.
> 
> Sure, will get back on this.
> 
>>
>> And if they actually need to be back to back, what ensures that
>> this is always called with interrupt disabled?
>>
>> You would also need to have them in the same asm block to avoid
>> the compiler reordering stuff.
> 
> Agreed, both the above constructs will be required to make sure that
> the instructions will be executed consecutively (if required).
> 


I checked this with our architects and it doesn't have to be in tight
loop. The TSBs are meant to be used with the PE in Trace prohibited
regions (which they are for TRBE and the KVM nvhe stub, TRFCR_ELx 
cleared). As long as that is honored, we are fine. I will update
the patch.

Kind regards
Suzuki