linux-kernel - [PATCH 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED

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Message-ID: <20210913121956.1776656-2-chenhuang5@huawei.com>
Date:   Mon, 13 Sep 2021 12:19:55 +0000
From:   Chen Huang <chenhuang5@...wei.com>
To:     Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>
CC:     Chen Huang <chenhuang5@...wei.com>,
        Kefeng Wang <wangkefeng.wang@...wei.com>,
        <linux-riscv@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH 1/2] riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS

The RISCV ISA can perform efficient unaligned memory accesses
in hardware. This patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS
for that.

Signed-off-by: Chen Huang <chenhuang5@...wei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@...wei.com>
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index aac669a6c3d8..6e70bf50b02a 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -81,6 +81,7 @@ config RISCV
 	select HAVE_DEBUG_KMEMLEAK
 	select HAVE_DMA_CONTIGUOUS if MMU
 	select HAVE_EBPF_JIT if MMU
+	select HAVE_EFFICIENT_UNALIGNED_ACCESS
 	select HAVE_FUNCTION_ERROR_INJECTION
 	select HAVE_FUTEX_CMPXCHG if FUTEX
 	select HAVE_GCC_PLUGINS
-- 
2.18.0.huawei.25