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Message-ID: <CAGXv+5FcTbaR2yXK3OB+iTgYy1OUpDt2FKQw7bA3nGdk4jKxZg@mail.gmail.com>
Date:   Tue, 14 Sep 2021 11:54:30 +0800
From:   Chen-Yu Tsai <wenst@...omium.org>
To:     Chun-Jie Chen <chun-jie.chen@...iatek.com>
Cc:     Matthias Brugger <matthias.bgg@...il.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Nicolas Boichat <drinkcat@...omium.org>,
        Rob Herring <robh+dt@...nel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        LKML <linux-kernel@...r.kernel.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@...ts.infradead.org>,
        linux-clk <linux-clk@...r.kernel.org>,
        Devicetree List <devicetree@...r.kernel.org>,
        srv_heupstream <srv_heupstream@...iatek.com>,
        Project_Global_Chrome_Upstream_Group 
        <Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [v3 07/24] clk: mediatek: Add MT8195 topckgen clock support

On Tue, Sep 14, 2021 at 10:17 AM Chun-Jie Chen
<chun-jie.chen@...iatek.com> wrote:
>
> Add MT8195 topckgen clock controller which provides muxes, dividers
> to handle variety clock selection in other IP blocks.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@...iatek.com>

Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>

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