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Message-ID: <CAGXv+5EeaodgMroPF==9ov3nNKNHs1WWHk3DqNWDRmb=Du+-Bg@mail.gmail.com>
Date: Tue, 14 Sep 2021 11:57:11 +0800
From: Chen-Yu Tsai <wenst@...omium.org>
To: Chun-Jie Chen <chun-jie.chen@...iatek.com>
Cc: Matthias Brugger <matthias.bgg@...il.com>,
Stephen Boyd <sboyd@...nel.org>,
Nicolas Boichat <drinkcat@...omium.org>,
Rob Herring <robh+dt@...nel.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
LKML <linux-kernel@...r.kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>,
linux-clk <linux-clk@...r.kernel.org>,
Devicetree List <devicetree@...r.kernel.org>,
srv_heupstream <srv_heupstream@...iatek.com>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [v3 09/24] clk: mediatek: Add MT8195 infrastructure clock support
On Tue, Sep 14, 2021 at 10:17 AM Chun-Jie Chen
<chun-jie.chen@...iatek.com> wrote:
>
> Add MT8195 infrastructure clock controller which provides
> clock gate control for basic IP like pwm, uart, spi and so on.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@...iatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>
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