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Date:   Thu, 16 Sep 2021 00:59:35 +0900
From:   Chanwoo Choi <cwchoi00@...il.com>
To:     Sam Protsenko <semen.protsenko@...aro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        Sylwester Nawrocki <s.nawrocki@...sung.com>,
        Paweł Chmiel <pawel.mikolaj.chmiel@...il.com>,
        Chanwoo Choi <cw00.choi@...sung.com>,
        Tomasz Figa <tomasz.figa@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>
Cc:     Ryu Euiyoul <ryu.real@...sung.com>, Tom Gall <tom.gall@...aro.org>,
        Sumit Semwal <sumit.semwal@...aro.org>,
        John Stultz <john.stultz@...aro.org>,
        Amit Pundir <amit.pundir@...aro.org>,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH 2/6] clk: samsung: clk-pll: Implement pll0822x PLL type

On 21. 9. 15. 오전 12:56, Sam Protsenko wrote:
> pll0822x PLL is used in Exynos850 SoC for top-level integer PLLs. The
> code was derived from very similar pll35xx type, with next differences:
> 
> 1. Lock time for pll0822x is 150*P_DIV, when for pll35xx it's 270*P_DIV
> 2. It's not suggested in Exynos850 TRM that S_DIV change doesn't require
>     performing PLL lock procedure (which is done in pll35xx
>     implementation)
> 
> When defining pll0822x type, CON3 register offset should be provided as
> a "con" parameter of PLL() macro, like this:
> 
>      PLL(pll_0822x, 0, "fout_shared0_pll", "oscclk",
>          PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
>          exynos850_shared0_pll_rates),
> 
> To define PLL rates table, one can use PLL_35XX_RATE() macro, e.g.:
> 
>      PLL_35XX_RATE(26 * MHZ, 1600 * MHZ, 800, 13, 0)
> 
> as it's completely appropriate for pl0822x type and there is no sense in
> duplicating that.
> 
> If bit #1 (MANUAL_PLL_CTRL) is not set in CON1 register, it won't be
> possible to set new rate, with next error showing in kernel log:
> 
>      Could not lock PLL fout_shared1_pll
> 
> That can happen for example if bootloader clears that bit beforehand.
> PLL driver doesn't account for that, so if MANUAL_PLL_CTRL bit was
> cleared, it's assumed it was done for a reason and it shouldn't be
> possible to change that PLL's rate at all.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@...aro.org>
> ---
>   drivers/clk/samsung/clk-pll.c | 91 +++++++++++++++++++++++++++++++++++
>   drivers/clk/samsung/clk-pll.h |  1 +
>   2 files changed, 92 insertions(+)
> 
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 5873a9354b50..03131b149c0b 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -415,6 +415,89 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = {
>   	.recalc_rate = samsung_pll36xx_recalc_rate,
>   };
>   
> +/*
> + * PLL0822x Clock Type
> + */
> +/* Maximum lock time can be 150 * PDIV cycles */
> +#define PLL0822X_LOCK_FACTOR		(150)
> +
> +#define PLL0822X_MDIV_MASK		(0x3FF)
> +#define PLL0822X_PDIV_MASK		(0x3F)
> +#define PLL0822X_SDIV_MASK		(0x7)
> +#define PLL0822X_MDIV_SHIFT		(16)
> +#define PLL0822X_PDIV_SHIFT		(8)
> +#define PLL0822X_SDIV_SHIFT		(0)
> +#define PLL0822X_LOCK_STAT_SHIFT	(29)
> +#define PLL0822X_ENABLE_SHIFT		(31)
> +
> +static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
> +						  unsigned long parent_rate)
> +{
> +	struct samsung_clk_pll *pll = to_clk_pll(hw);
> +	u32 mdiv, pdiv, sdiv, pll_con3;
> +	u64 fvco = parent_rate;
> +
> +	pll_con3 = readl_relaxed(pll->con_reg);
> +	mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
> +	pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
> +	sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
> +
> +	fvco *= mdiv;
> +	do_div(fvco, (pdiv << sdiv));
> +
> +	return (unsigned long)fvco;
> +}
> +
> +static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate,
> +				     unsigned long prate)
> +{
> +	const struct samsung_pll_rate_table *rate;
> +	struct samsung_clk_pll *pll = to_clk_pll(hw);
> +	u32 pll_con3;
> +
> +	/* Get required rate settings from table */
> +	rate = samsung_get_pll_settings(pll, drate);
> +	if (!rate) {
> +		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
> +			drate, clk_hw_get_name(hw));
> +		return -EINVAL;
> +	}
> +
> +	/* Change PLL PMS values */
> +	pll_con3 = readl_relaxed(pll->con_reg);
> +	pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) |
> +			(PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) |
> +			(PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT));
> +	pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) |
> +			(rate->pdiv << PLL0822X_PDIV_SHIFT) |
> +			(rate->sdiv << PLL0822X_SDIV_SHIFT);
> +
> +	/* Set PLL lock time */
> +	writel_relaxed(rate->pdiv * PLL0822X_LOCK_FACTOR,
> +			pll->lock_reg);
> +
> +	/* Write PMS values */
> +	writel_relaxed(pll_con3, pll->con_reg);
> +
> +	/* Wait for PLL lock if the PLL is enabled */
> +	if (pll_con3 & BIT(pll->enable_offs))
> +		return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
> +
> +	return 0;
> +}
> +
> +static const struct clk_ops samsung_pll0822x_clk_ops = {
> +	.recalc_rate = samsung_pll0822x_recalc_rate,
> +	.round_rate = samsung_pll_round_rate,
> +	.set_rate = samsung_pll0822x_set_rate,
> +	.enable = samsung_pll3xxx_enable,
> +	.disable = samsung_pll3xxx_disable,
> +};
> +
> +static const struct clk_ops samsung_pll0822x_clk_min_ops = {
> +	.recalc_rate = samsung_pll0822x_recalc_rate,
> +};
> +
>   /*
>    * PLL45xx Clock Type
>    */
> @@ -1296,6 +1379,14 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
>   		else
>   			init.ops = &samsung_pll35xx_clk_ops;
>   		break;
> +	case pll_0822x:
> +		pll->enable_offs = PLL0822X_ENABLE_SHIFT;
> +		pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
> +		if (!pll->rate_table)
> +			init.ops = &samsung_pll0822x_clk_min_ops;
> +		else
> +			init.ops = &samsung_pll0822x_clk_ops;
> +		break;
>   	case pll_4500:
>   		init.ops = &samsung_pll45xx_clk_min_ops;
>   		break;
> diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
> index 79e41c226b90..213e94a97f23 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -36,6 +36,7 @@ enum samsung_pll_type {
>   	pll_1451x,
>   	pll_1452x,
>   	pll_1460x,
> +	pll_0822x,
>   };
>   
>   #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
> 

Even if I have not Exynos850 TRM, it looks good to me. Thanks.

Acked-by: Chanwoo Choi <cw00.choi@...sung.com>

-- 
Best Regards,
Samsung Electronics
Chanwoo Choi

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