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Message-ID: <c534c85e-d5a6-43e0-25f6-3d0ff3bc1f68@gmail.com>
Date: Thu, 16 Sep 2021 01:11:24 +0900
From: Chanwoo Choi <cwchoi00@...il.com>
To: Sam Protsenko <semen.protsenko@...aro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Paweł Chmiel <pawel.mikolaj.chmiel@...il.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Tomasz Figa <tomasz.figa@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>
Cc: Ryu Euiyoul <ryu.real@...sung.com>, Tom Gall <tom.gall@...aro.org>,
Sumit Semwal <sumit.semwal@...aro.org>,
John Stultz <john.stultz@...aro.org>,
Amit Pundir <amit.pundir@...aro.org>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH 3/6] clk: samsung: clk-pll: Implement pll0831x PLL type
On 21. 9. 15. 오전 12:56, Sam Protsenko wrote:
> pll0831x PLL is used in Exynos850 SoC for top-level fractional PLLs. The
> code was derived from very similar pll36xx type, with next differences:
>
> 1. Lock time for pll0831x is 500*P_DIV, when for pll36xx it's 3000*P_DIV
> 2. It's not suggested in Exynos850 TRM that S_DIV change doesn't require
> performing PLL lock procedure (which is done in pll36xx
> implementation)
> 3. The offset from PMS-values register to K-value register is 0x8 for
> pll0831x, when for pll36xx it's 0x4
>
> When defining pll0831x type, CON3 register offset should be provided as
> a "con" parameter of PLL() macro, like this:
>
> PLL(pll_0831x, 0, "fout_mmc_pll", "oscclk",
> PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, pll0831x_26mhz_tbl),
>
> To define PLL rates table, one can use PLL_36XX_RATE() macro, e.g.:
>
> PLL_36XX_RATE(26 * MHZ, 799999877, 31, 1, 0, -15124)
>
> as it's completely appropriate for pl0831x type and there is no sense in
> duplicating that.
>
> If bit #1 (MANUAL_PLL_CTRL) is not set in CON1 register, it won't be
> possible to set new rate, with next error showing in kernel log:
>
> Could not lock PLL fout_mmc_pll
>
> That can happen for example if bootloader clears that bit beforehand.
> PLL driver doesn't account for that, so if MANUAL_PLL_CTRL bit was
> cleared, it's assumed it was done for a reason and it shouldn't be
> possible to change that PLL's rate at all.
>
> Signed-off-by: Sam Protsenko <semen.protsenko@...aro.org>
> ---
> drivers/clk/samsung/clk-pll.c | 105 ++++++++++++++++++++++++++++++++++
> drivers/clk/samsung/clk-pll.h | 1 +
> 2 files changed, 106 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 03131b149c0b..83d1b03647db 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -498,6 +498,103 @@ static const struct clk_ops samsung_pll0822x_clk_min_ops = {
> .recalc_rate = samsung_pll0822x_recalc_rate,
> };
>
> +/*
> + * PLL0831x Clock Type
> + */
> +/* Maximum lock time can be 500 * PDIV cycles */
> +#define PLL0831X_LOCK_FACTOR (500)
> +
> +#define PLL0831X_KDIV_MASK (0xFFFF)
> +#define PLL0831X_MDIV_MASK (0x1FF)
> +#define PLL0831X_PDIV_MASK (0x3F)
> +#define PLL0831X_SDIV_MASK (0x7)
> +#define PLL0831X_MDIV_SHIFT (16)
> +#define PLL0831X_PDIV_SHIFT (8)
> +#define PLL0831X_SDIV_SHIFT (0)
> +#define PLL0831X_KDIV_SHIFT (0)
> +#define PLL0831X_LOCK_STAT_SHIFT (29)
> +#define PLL0831X_ENABLE_SHIFT (31)
> +
> +static unsigned long samsung_pll0831x_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct samsung_clk_pll *pll = to_clk_pll(hw);
> + u32 mdiv, pdiv, sdiv, pll_con3, pll_con5;
> + s16 kdiv;
> + u64 fvco = parent_rate;
> +
> + pll_con3 = readl_relaxed(pll->con_reg);
> + pll_con5 = readl_relaxed(pll->con_reg + 8);
> + mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK;
> + pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK;
> + sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK;
> + kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK);
> +
> + fvco *= (mdiv << 16) + kdiv;
> + do_div(fvco, (pdiv << sdiv));
> + fvco >>= 16;
> +
> + return (unsigned long)fvco;
> +}
> +
> +static int samsung_pll0831x_set_rate(struct clk_hw *hw, unsigned long drate,
> + unsigned long parent_rate)
> +{
> + const struct samsung_pll_rate_table *rate;
> + struct samsung_clk_pll *pll = to_clk_pll(hw);
> + u32 pll_con3, pll_con5;
> +
> + /* Get required rate settings from table */
> + rate = samsung_get_pll_settings(pll, drate);
> + if (!rate) {
> + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
> + drate, clk_hw_get_name(hw));
> + return -EINVAL;
> + }
> +
> + pll_con3 = readl_relaxed(pll->con_reg);
> + pll_con5 = readl_relaxed(pll->con_reg + 8);
> +
> + /* Change PLL PMSK values */
> + pll_con3 &= ~((PLL0831X_MDIV_MASK << PLL0831X_MDIV_SHIFT) |
> + (PLL0831X_PDIV_MASK << PLL0831X_PDIV_SHIFT) |
> + (PLL0831X_SDIV_MASK << PLL0831X_SDIV_SHIFT));
> + pll_con3 |= (rate->mdiv << PLL0831X_MDIV_SHIFT) |
> + (rate->pdiv << PLL0831X_PDIV_SHIFT) |
> + (rate->sdiv << PLL0831X_SDIV_SHIFT);
> + pll_con5 &= ~(PLL0831X_KDIV_MASK << PLL0831X_KDIV_SHIFT);
> + /*
> + * kdiv is 16-bit 2's complement (s16), but stored as unsigned int.
> + * Cast it to u16 to avoid leading 0xffff's in case of negative value.
> + */
> + pll_con5 |= ((u16)rate->kdiv << PLL0831X_KDIV_SHIFT);
> +
> + /* Set PLL lock time */
> + writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg);
> +
> + /* Write PMSK values */
> + writel_relaxed(pll_con3, pll->con_reg);
> + writel_relaxed(pll_con5, pll->con_reg + 8);
> +
> + /* Wait for PLL lock if the PLL is enabled */
> + if (pll_con3 & BIT(pll->enable_offs))
> + return samsung_pll_lock_wait(pll, BIT(pll->lock_offs));
> +
> + return 0;
> +}
> +
> +static const struct clk_ops samsung_pll0831x_clk_ops = {
> + .recalc_rate = samsung_pll0831x_recalc_rate,
> + .set_rate = samsung_pll0831x_set_rate,
> + .round_rate = samsung_pll_round_rate,
> + .enable = samsung_pll3xxx_enable,
> + .disable = samsung_pll3xxx_disable,
> +};
> +
> +static const struct clk_ops samsung_pll0831x_clk_min_ops = {
> + .recalc_rate = samsung_pll0831x_recalc_rate,
> +};
> +
> /*
> * PLL45xx Clock Type
> */
> @@ -1407,6 +1504,14 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
> else
> init.ops = &samsung_pll36xx_clk_ops;
> break;
> + case pll_0831x:
> + pll->enable_offs = PLL0831X_ENABLE_SHIFT;
> + pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT;
> + if (!pll->rate_table)
> + init.ops = &samsung_pll0831x_clk_min_ops;
> + else
> + init.ops = &samsung_pll0831x_clk_ops;
> + break;
> case pll_6552:
> case pll_6552_s3c2416:
> init.ops = &samsung_pll6552_clk_ops;
> diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
> index 213e94a97f23..a739f2b7ae80 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -37,6 +37,7 @@ enum samsung_pll_type {
> pll_1452x,
> pll_1460x,
> pll_0822x,
> + pll_0831x,
> };
>
> #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
>
Acked-by: Chanwoo Choi <cw00.choi@...sung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
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