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Date:   Sat, 18 Sep 2021 22:17:13 +0800
From:   Jisheng Zhang <jszhang3@...l.ustc.edu.cn>
To:     Kefeng Wang <wangkefeng.wang@...wei.com>
Cc:     Chen Huang <chenhuang5@...wei.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Darius Rad <darius@...espec.com>,
        <linux-riscv@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 0/2] riscv: improve unaligned memory accesses

On Sat, 18 Sep 2021 09:14:05 +0800
Kefeng Wang <wangkefeng.wang@...wei.com> wrote:

> On 2021/9/17 22:14, Jisheng Zhang wrote:
> > On Thu, 16 Sep 2021 13:08:53 +0000
> > Chen Huang <chenhuang5@...wei.com> wrote:
> >  
> >> The patchset improves RISCV unaligned memory accesses, selects
> >> HAVE_EFFICIENT_UNALIGNED_ACCESS if CPU_HAS_NO_UNALIGNED not
> >> enabled and supports DCACHE_WORD_ACCESS to improve the efficiency
> >> of unaligned memory accesses.
> >>
> >> If CPU don't support unaligned memory accesses for now, please
> >> select CONFIG_CPU_HAS_NO_UNALIGNED. For I don't know which CPU
> >> don't support unaligned memory accesses, I don't choose the
> >> CONFIG for them.  
> > This will break unified kernel Image for riscv. Obviously, we will have
> > two images for efficient unaligned access platforms and non-efficient
> > unaligned access platforms. IMHO, we may need alternative mechanism or
> > something else to dynamically enable related code path.  
> 
> it won't break unified kernel Image for riscv, if one SoC choose
> 
> CPU_HAS_NO_UNALIGNED, the single Image won't support unaligned memory

the "unified" means the kernel Image has to support all RV64GC or RV32GC SoCs.
To make the Image works for both efficient unaligned access and inefficient
unaligned access, I think we'd better make "inefficient unaligned access"
default behavior, the use alternative etc. tech to patch related code path
for efficient unaligned access.


> 
> accesses, indeed, it depends on the CONFIG, and now, arm/powerpc/m68k has

linux Distributions doesn't have enough background of which config options
must be enabled.

> 
> similar configuration.

I have little knowledge of powerpc or m68k, but there are serveral different
defconfig files for arm, for example multi_v7_defconfig and multi_v5_defconfig.
The previous v7 version enables HAVE_EFFICIENT_UNALIGNED_ACCESS while
the later v5 doesn't. Will you persuade riscv maintainers to accept one more
defconfig file?

Thanks

> 
> Yes,  it could be an optimization via alternative mechanism or something 
> else to
> 
> dynamically enable related code path later.
> 
> >
> > Regards
> >  
> >> Changes since v1:
> >>   - As Darius Rad and Jisheng Zhang mentioned, some CPUs don't support
> >>     unaligned memory accesses, add an option for CPUs to choose it or not.
> >>
> >> Chen Huang (2):
> >>    riscv: support HAVE_EFFICIENT_UNALIGNED_ACCESS
> >>    riscv: Support DCACHE_WORD_ACCESS
> >>
> >>   arch/riscv/Kconfig                      |  5 ++++
> >>   arch/riscv/include/asm/word-at-a-time.h | 37 +++++++++++++++++++++++++
> >>   2 files changed, 42 insertions(+)
> >>  
> >
> > .
> >  


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