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Message-ID: <YUztDv/KbKVAY7cB@robh.at.kernel.org>
Date: Thu, 23 Sep 2021 16:09:34 -0500
From: Rob Herring <robh@...nel.org>
To: Dmitry Osipenko <digetx@...il.com>
Cc: linux-pm@...r.kernel.org, linux-mmc@...r.kernel.org,
Lucas Stach <dev@...xeye.de>,
Ulf Hansson <ulf.hansson@...aro.org>,
Mikko Perttunen <mperttunen@...dia.com>,
linux-kernel@...r.kernel.org, Peter Chen <peter.chen@...nel.org>,
Mark Brown <broonie@...nel.org>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>, David Heidelberg <david@...t.cz>,
Jonathan Hunter <jonathanh@...dia.com>,
Rob Herring <robh+dt@...nel.org>,
Stephen Boyd <sboyd@...nel.org>, linux-tegra@...r.kernel.org,
Richard Weinberger <richard@....at>,
Miquel Raynal <miquel.raynal@...tlin.com>,
linux-usb@...r.kernel.org, linux-clk@...r.kernel.org,
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linux-staging@...ts.linux.dev, Stefan Agner <stefan@...er.ch>,
Vignesh Raghavendra <vigneshr@...com>,
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Thierry Reding <thierry.reding@...il.com>,
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devicetree@...r.kernel.org, Lee Jones <lee.jones@...aro.org>,
Adrian Hunter <adrian.hunter@...el.com>
Subject: Re: [PATCH v12 05/35] dt-bindings: clock: tegra-car: Document new
clock sub-nodes
On Mon, 20 Sep 2021 21:11:15 +0300, Dmitry Osipenko wrote:
> Document sub-nodes which describe Tegra SoC clocks that require a higher
> voltage of the core power domain in order to operate properly on a higher
> clock rates. Each node contains a phandle to OPP table and power domain.
>
> The root PLLs and system clocks don't have any specific device dedicated
> to them, clock controller is in charge of managing power for them.
>
> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
> ---
> .../bindings/clock/nvidia,tegra20-car.yaml | 37 +++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
Reviewed-by: Rob Herring <robh@...nel.org>
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