linux-kernel - Re: [RESEND PATCH] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs

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Message-ID: <CAJZ5v0iS+TnkoqCxLa92Na=By53PXY-qW=k4utr_84KYaw+sVQ@mail.gmail.com>
Date:   Fri, 24 Sep 2021 18:48:48 +0200
From:   "Rafael J. Wysocki" <rafael@...nel.org>
To:     Deepak Sharma <deepak.sharma@....com>
Cc:     "Rafael J. Wysocki" <rafael@...nel.org>,
        Len Brown <len.brown@...el.com>, Pavel Machek <pavel@....cz>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        "the arch/x86 maintainers" <x86@...nel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linux PM <linux-pm@...r.kernel.org>
Subject: Re: [RESEND PATCH] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs

On Fri, Sep 24, 2021 at 8:12 AM Deepak Sharma <deepak.sharma@....com> wrote:
>
> All Zen or newer CPU which support C3 shares cache. Its not necessary to
> flush the caches in software before entering C3. This will cause drop in
> performance for the cores which share some caches. ARB_DIS is not used
> with current AMD C state implementation. So set related flags correctly.
>
> Signed-off-by: Deepak Sharma <deepak.sharma@....com>

I'm planning to take this one unless the x86 maintainers have concerns, thanks.

> ---
>  arch/x86/kernel/acpi/cstate.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
> index 7de599eba7f0..7945eae5b315 100644
> --- a/arch/x86/kernel/acpi/cstate.c
> +++ b/arch/x86/kernel/acpi/cstate.c
> @@ -79,6 +79,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
>                  */
>                 flags->bm_control = 0;
>         }
> +       if (c->x86_vendor == X86_VENDOR_AMD && c->x86 >= 0x17) {
> +               /*
> +                * For all AMD Zen or newer CPUs that support C3, caches
> +                * should not be flushed by software while entering C3
> +                * type state. Set bm->check to 1 so that kernel doesn't
> +                * need to execute cache flush operation.
> +                */
> +               flags->bm_check = 1;
> +               /*
> +                * In current AMD C state implementation ARB_DIS is no longer
> +                * used. So set bm_control to zero to indicate ARB_DIS is not
> +                * required while entering C3 type state.
> +                */
> +               flags->bm_control = 0;
> +       }
>  }
>  EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
>
> --
> 2.25.1
>