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Date:   Sun, 26 Sep 2021 17:12:59 +0200
From:   Thomas Gleixner <tglx@...utronix.de>
To:     "Rafael J. Wysocki" <rafael@...nel.org>,
        Deepak Sharma <deepak.sharma@....com>
Cc:     "Rafael J. Wysocki" <rafael@...nel.org>,
        Len Brown <len.brown@...el.com>, Pavel Machek <pavel@....cz>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        the arch/x86 maintainers <x86@...nel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linux PM <linux-pm@...r.kernel.org>
Subject: Re: [RESEND PATCH] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs

On Fri, Sep 24 2021 at 18:48, Rafael J. Wysocki wrote:

> On Fri, Sep 24, 2021 at 8:12 AM Deepak Sharma <deepak.sharma@....com> wrote:
>>
>> All Zen or newer CPU which support C3 shares cache. Its not necessary to
>> flush the caches in software before entering C3. This will cause drop in
>> performance for the cores which share some caches. ARB_DIS is not used
>> with current AMD C state implementation. So set related flags correctly.
>>
>> Signed-off-by: Deepak Sharma <deepak.sharma@....com>
>
> I'm planning to take this one unless the x86 maintainers have concerns, thanks.

Acked-by: Thomas Gleixner <tglx@...utronix.de>

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