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Message-ID: <YVG46L++WPBAHxQv@zn.tnic>
Date:   Mon, 27 Sep 2021 14:28:24 +0200
From:   Borislav Petkov <bp@...en8.de>
To:     Paolo Bonzini <pbonzini@...hat.com>
Cc:     Babu Moger <babu.moger@....com>, tglx@...utronix.de,
        mingo@...hat.com, x86@...nel.org, hpa@...or.com, seanjc@...gle.com,
        vkuznets@...hat.com, wanpengli@...cent.com, jmattson@...gle.com,
        joro@...tes.org, tony.luck@...el.com, peterz@...radead.org,
        kyung.min.park@...el.com, wei.huang2@....com, jgross@...e.com,
        andrew.cooper3@...rix.com, linux-kernel@...r.kernel.org,
        kvm@...r.kernel.org
Subject: Re: [PATCH] KVM: x86: Expose Predictive Store Forwarding Disable

On Mon, Sep 27, 2021 at 02:14:52PM +0200, Paolo Bonzini wrote:
> Right, not which MSR to write but which value to write.  It doesn't know
> that the PSF disable bit is valid unless the corresponding CPUID bit is set.

There's no need for the separate PSF CPUID bit yet. We have decided for
now to not control PSF separately but disable it through SSB. Please
follow this thread:

https://lore.kernel.org/all/20210904172334.lfjyqi4qfzvbxef7@treble/T/#u

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

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