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Date:   Mon, 27 Sep 2021 14:54:08 +0200
From:   Paolo Bonzini <pbonzini@...hat.com>
To:     Borislav Petkov <bp@...en8.de>
Cc:     Babu Moger <babu.moger@....com>, tglx@...utronix.de,
        mingo@...hat.com, x86@...nel.org, hpa@...or.com, seanjc@...gle.com,
        vkuznets@...hat.com, wanpengli@...cent.com, jmattson@...gle.com,
        joro@...tes.org, tony.luck@...el.com, peterz@...radead.org,
        kyung.min.park@...el.com, wei.huang2@....com, jgross@...e.com,
        andrew.cooper3@...rix.com, linux-kernel@...r.kernel.org,
        kvm@...r.kernel.org
Subject: Re: [PATCH] KVM: x86: Expose Predictive Store Forwarding Disable

On 27/09/21 14:28, Borislav Petkov wrote:
> On Mon, Sep 27, 2021 at 02:14:52PM +0200, Paolo Bonzini wrote:
>> Right, not which MSR to write but which value to write.  It doesn't know
>> that the PSF disable bit is valid unless the corresponding CPUID bit is set.
> 
> There's no need for the separate PSF CPUID bit yet. We have decided for
> now to not control PSF separately but disable it through SSB. Please
> follow this thread:

There are other guests than Linux.  This patch is just telling userspace 
that KVM knows what the PSFD bit is.  It is also possible to expose the 
bit in KVM without having any #define in cpufeatures.h or without the 
kernel using it.  For example KVM had been exposing FSGSBASE long before 
Linux supported it.

That said, the patch is incomplete because it should also add the new 
CPUID bit to guest_has_spec_ctrl_msr (what KVM *really* cares about is 
not the individual bits, only whether SPEC_CTRL exists at all).

Paolo

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