linux-kernel - [PATCH v1 2/3] serial:8250:Add RS485 support for MCHP PCI1XXXX UART

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20210929113049.64557-3-LakshmiPraveen.Kopparthi@microchip.com>
Date:   Wed, 29 Sep 2021 17:00:48 +0530
From:   LakshmiPraveen Kopparthi <LakshmiPraveen.Kopparthi@...rochip.com>
To:     <gregkh@...uxfoundation.org>, <jirislaby@...nel.org>,
        <andriy.shevchenko@...ux.intel.com>, <macro@...am.me.uk>,
        <zev@...ilderbeest.net>, <vigneshr@...com>,
        <linux-serial@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC:     <UNGLinuxDriver@...rochip.com>
Subject: [PATCH v1 2/3] serial:8250:Add RS485 support for MCHP PCI1XXXX UART

UART module has built in support to control the RTS line. This patch 
adds the support to configure the HW control of RTS.

Signed-off-by: LakshmiPraveen Kopparthi <LakshmiPraveen.Kopparthi@...rochip.com>
---
 drivers/tty/serial/8250/8250_pci.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
index 12a3e0bd50aa..b06374fc6212 100644
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -1887,11 +1887,39 @@ pci_moxa_setup(struct serial_private *priv,
 #define PCI_SUBDEVICE_ID_MCHP_PCI1XXXX_1P3	0x000F
 
 #define UART_ACTV_REG 0x11
+#define ADC_CFG_REG 0x40
 #define UART_PCI_CTRL_REG 0x80
 #define UART_WAKE_REG 0x8C
 #define UART_WAKE_MASK_REG 0x90
 #define UART_RESET_REG 0x94
 
+#define ADC_EN BIT(0)
+#define ADC_PIN_SEL BIT(1)
+#define ADC_POLARITY BIT(2)
+
+static int mchp_pci1xxxx_rs485_config(struct uart_port *port,
+				      struct serial_rs485 *rs485)
+{
+	u8 data = 0;
+
+	memset(rs485->padding, 0, sizeof(rs485->padding));
+	rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
+
+	if (rs485->flags & SER_RS485_ENABLED) {
+		data = ADC_EN | ADC_PIN_SEL;
+		if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) {
+			data |= ADC_POLARITY;
+			rs485->flags |=  SER_RS485_RTS_AFTER_SEND;
+		}
+	}
+
+	rs485->delay_rts_after_send = 0;
+	rs485->delay_rts_before_send = 0;
+	writeb(data, (port->membase + ADC_CFG_REG));
+	port->rs485 = *rs485;
+	return 0;
+}
+
 static char pci1xxxx_port_suspend(int line)
 {
 	struct uart_8250_port *up = serial8250_get_port(line);
@@ -2073,6 +2101,7 @@ static int mchp_pci1xxxx_setup(struct serial_private *priv,
 	offset = first_offset + idx * board->uart_offset;
 	port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST;
 	port->port.type = PORT_MCHP16550A;
+	port->port.rs485_config = mchp_pci1xxxx_rs485_config;
 	ret = setup_port(priv, port, bar, offset, board->reg_shift);
 	if (ret < 0)
 		return ret;
-- 
2.25.1