linux-kernel - Re: [PATCH v17 08/15] arm64: kexec: configure EL2 vectors for kexec

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Thu, 30 Sep 2021 07:59:07 -0400
From:   Pasha Tatashin <pasha.tatashin@...een.com>
To:     Will Deacon <will@...nel.org>
Cc:     James Morris <jmorris@...ei.org>, Sasha Levin <sashal@...nel.org>,
        "Eric W. Biederman" <ebiederm@...ssion.com>,
        kexec mailing list <kexec@...ts.infradead.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Jonathan Corbet <corbet@....net>,
        Catalin Marinas <catalin.marinas@....com>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Marc Zyngier <maz@...nel.org>,
        James Morse <james.morse@....com>,
        Vladimir Murzin <vladimir.murzin@....com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        linux-mm <linux-mm@...ck.org>,
        Mark Rutland <mark.rutland@....com>, steve.capper@....com,
        rfontana@...hat.com, Thomas Gleixner <tglx@...utronix.de>,
        Selin Dag <selindag@...il.com>,
        Tyler Hicks <tyhicks@...ux.microsoft.com>,
        Pingfan Liu <kernelfans@...il.com>,
        Andrew Morton <akpm@...ux-foundation.org>,
        madvenka@...ux.microsoft.com
Subject: Re: [PATCH v17 08/15] arm64: kexec: configure EL2 vectors for kexec

On Thu, Sep 30, 2021 at 4:16 AM Will Deacon <will@...nel.org> wrote:
>
> On Wed, Sep 29, 2021 at 11:54:55PM -0400, Pasha Tatashin wrote:
> > > > +/* Allocates pages for kexec page table */
> > > > +static void *kexec_page_alloc(void *arg)
> > > > +{
> > > > +     struct kimage *kimage = (struct kimage *)arg;
> > > > +     struct page *page = kimage_alloc_control_pages(kimage, 0);
> > > > +
> > > > +     if (!page)
> > > > +             return NULL;
> > > > +
> > > > +     memset(page_address(page), 0, PAGE_SIZE);
> > >
> > > Hmm, I think we might be missing barriers here to ensure that the zeroes
> > > are visible to the page-table walker before we plumb the page into the
> > > page-table.
> > >
> > > Usually, that's taken care of by the smp_wmb() in __pXX_alloc() but I
> > > can't see that here. Is it hiding?
> >
> > Based on the comment in __pte_alloc() that smp_wmb() is needed in
> > order to synchronize pte setup with other cpus prior to making it
> > visible to them. This is not needed here. First, by the time these
> > page tables are used the other cpus are offlined (kexec reboot code is
> > single threaded). Second, we never insert any entry into a page table
> > that is actively used by any cpu.
>
> I think the comment there is wrong, but the barrier is still necessary.
> How else do you guarantee that the page-table walker reads the zeroes from
> the memset?

True, good point. We are still safe because we have the following:
cpu_install_ttbr0() is used to load trans_pgd tables both in kexec and
hibernate cases.

cpu_install_ttbr0 has: local_flush_tlb_all()

dsb(nshst);   // Ensure prior page-table updates have completed
__tlbi(vmalle1);  // Invalidate the TLB
dsb(nsh);   // Ensure the TLB invalidation has completed
isb();  // Discard any instructions fetched from the old mapping

Pasha