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Message-Id: <6d0856b6953765463aac43fbd641d26f19dc7e11.1633369560.git.naveennaidu479@gmail.com>
Date: Mon, 4 Oct 2021 23:29:31 +0530
From: Naveen Naidu <naveennaidu479@...il.com>
To: bhelgaas@...gle.com, tsbogend@...ha.franken.de
Cc: Naveen Naidu <naveennaidu479@...il.com>,
linux-kernel-mentees@...ts.linuxfoundation.org,
skhan@...uxfoundation.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, linux-mips@...r.kernel.org
Subject: [PATCH 5/6] MIPS: OCTEON: Remove redundant ECRC Generation Enable
e8635b484f64 ("MIPS: Add Cavium OCTEON PCI support.") added MIPS
specific code to enable PCIe and AER error reporting (*irrespective
of CONFIG_PCIEAER value*) because PCI core didn't do that at the time.
Currently when CONFIG_PCIEAER=y, ECRC generation is enabled by
pcie_set_ecrc_checking() in the aer_probe() path.
It is now no longer necessary for Octeon code to enable ECRC since
it's done when PCIe bus loads the AER service driver.
Signed-off-by: Naveen Naidu <naveennaidu479@...il.com>
---
arch/mips/pci/pci-octeon.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index a82cf48f00ab..b973fc464c21 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -124,15 +124,6 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
*/
/* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
- /* Advanced Error Capabilities */
- pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
- /* ECRC Generation Enable */
- if (config & PCI_ERR_CAP_ECRC_GENC)
- config |= PCI_ERR_CAP_ECRC_GENE;
- /* ECRC Check Enable */
- if (config & PCI_ERR_CAP_ECRC_CHKC)
- config |= PCI_ERR_CAP_ECRC_CHKE;
- pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
/* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
/* Report all errors to the root complex */
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
--
2.25.1
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