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Message-ID: <CAE-0n50CBhdq3fbtygfzb0m8+bz3244-mYwCtVPjs_CfNaK_NQ@mail.gmail.com>
Date: Mon, 4 Oct 2021 21:11:47 -0400
From: Stephen Boyd <swboyd@...omium.org>
To: Prasad Malisetty <pmaliset@...eaurora.org>, agross@...nel.org,
bhelgaas@...gle.com, bjorn.andersson@...aro.org,
lorenzo.pieralisi@....com, robh+dt@...nel.org, svarbanov@...sol.com
Cc: devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-usb@...r.kernel.org, linux-kernel@...r.kernel.org,
dianders@...omium.org, mka@...omium.org, vbadigan@...eaurora.org,
sallenki@...eaurora.org, manivannan.sadhasivam@...aro.org,
linux-pci@...r.kernel.org
Subject: Re: [PATCH v10 2/5] arm64: dts: qcom: sc7280: Add PCIe and PHY
related nodes
Quoting Prasad Malisetty (2021-10-04 12:41:25)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 39635da..e4bbf48 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2676,6 +2787,12 @@
> gpio-ranges = <&tlmm 0 0 175>;
> wakeup-parent = <&pdc>;
>
> + pcie1_default_state: pcie1-default-state {
Maybe call the node pcie1_clkreq_n: pcie1-clkreq-n as it's now only for
the clkreq function.
> + pins = "gpio79";
> + function = "pcie1_clkreqn";
> + bias-pull-up;
> + };
> +
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