linux-kernel - Re: [x86] Kernel v5.14 series panic on Celeron Mendocino CPU

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Message-ID: <YV2l+1oIGd2p/Gt5@zn.tnic>
Date:   Wed, 6 Oct 2021 15:34:51 +0200
From:   Borislav Petkov <bp@...en8.de>
To:     Ser Olmy <ser.olmy@...tonmail.com>
Cc:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        x86-ml <x86@...nel.org>
Subject: Re: [x86] Kernel v5.14 series panic on Celeron Mendocino CPU

On Wed, Oct 06, 2021 at 12:42:47AM +0000, Ser Olmy wrote:
> Sure:

Thx.

> [   21.670972] fpu->state.fxsave.mxcsr: 0xb7be13b4, mxcsr_feature_mask: 0xffbf
> [   21.754383] WARNING: CPU: 0 PID: 1 at arch/x86/kernel/fpu/signal.c:384 __fpu_restore_sig+0x51f/0x540

As tglx expected.

I guess this fixes your issue (replace with previous diff pls):

---
diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c
index 445c57c9c539..684be34d4609 100644
--- a/arch/x86/kernel/fpu/signal.c
+++ b/arch/x86/kernel/fpu/signal.c
@@ -379,9 +379,8 @@ static int __fpu_restore_sig(void __user *buf, void __user *buf_fx,
 				     sizeof(fpu->state.fxsave)))
 			return -EFAULT;
 
-		/* Reject invalid MXCSR values. */
-		if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask)
-			return -EINVAL;
+		/* Mask out reserved MXCSR bits. */
+		fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
 
 		/* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */
 		if (use_xsave())

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette