linux-kernel - Re: [PATCH v3 17/17] arm64: Add HWCAP for self-synchronising virtual counter

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Date:   Mon, 11 Oct 2021 12:00:09 +0100
From:   Will Deacon <will@...nel.org>
To:     Marc Zyngier <maz@...nel.org>
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Mark Rutland <mark.rutland@....com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Peter Shier <pshier@...gle.com>,
        Raghavendra Rao Ananta <rananta@...gle.com>,
        Ricardo Koller <ricarkol@...gle.com>,
        Oliver Upton <oupton@...gle.com>,
        Catalin Marinas <catalin.marinas@....com>,
        Linus Walleij <linus.walleij@...aro.org>,
        kernel-team@...roid.com
Subject: Re: [PATCH v3 17/17] arm64: Add HWCAP for self-synchronising virtual
 counter

On Sun, Oct 10, 2021 at 12:43:06PM +0100, Marc Zyngier wrote:
> Since userspace can make use of the CNTVSS_EL0 instruction, expose
> it via a HWCAP.
> 
> Suggested-by: Will Deacon <will@...nel.org>
> Signed-off-by: Marc Zyngier <maz@...nel.org>
> ---
>  Documentation/arm64/elf_hwcaps.rst  | 4 ++++
>  arch/arm64/include/asm/hwcap.h      | 1 +
>  arch/arm64/include/uapi/asm/hwcap.h | 1 +
>  arch/arm64/kernel/cpufeature.c      | 3 ++-
>  arch/arm64/kernel/cpuinfo.c         | 1 +
>  5 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst
> index ec1a5a63c1d0..af106af8e1c0 100644
> --- a/Documentation/arm64/elf_hwcaps.rst
> +++ b/Documentation/arm64/elf_hwcaps.rst
> @@ -247,6 +247,10 @@ HWCAP2_MTE
>      Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described
>      by Documentation/arm64/memory-tagging-extension.rst.
>  
> +HWCAP2_ECV
> +
> +    Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001.
> +
>  4. Unused AT_HWCAP bits
>  -----------------------
>  
> diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
> index 8c129db8232a..b100e0055eab 100644
> --- a/arch/arm64/include/asm/hwcap.h
> +++ b/arch/arm64/include/asm/hwcap.h
> @@ -105,6 +105,7 @@
>  #define KERNEL_HWCAP_RNG		__khwcap2_feature(RNG)
>  #define KERNEL_HWCAP_BTI		__khwcap2_feature(BTI)
>  #define KERNEL_HWCAP_MTE		__khwcap2_feature(MTE)
> +#define KERNEL_HWCAP_ECV		__khwcap2_feature(ECV)
>  
>  /*
>   * This yields a mask that user programs can use to figure out what
> diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h
> index b8f41aa234ee..7b23b16f21ce 100644
> --- a/arch/arm64/include/uapi/asm/hwcap.h
> +++ b/arch/arm64/include/uapi/asm/hwcap.h
> @@ -75,5 +75,6 @@
>  #define HWCAP2_RNG		(1 << 16)
>  #define HWCAP2_BTI		(1 << 17)
>  #define HWCAP2_MTE		(1 << 18)
> +#define HWCAP2_ECV		(1 << 19)
>  
>  #endif /* _UAPI__ASM_HWCAP_H */
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 26b11ce8fff6..97ed37c6ce5e 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -279,7 +279,7 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
>  };
>  
>  static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
> -	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),

This needs an update to Documentation/arm64/cpu-feature-registers.rst.

With that:

Acked-by: Will Deacon <will@...nel.org>

Will