linux-kernel - Re: [PATCH v3 00/17] clocksource/arm_arch

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Message-ID: <20211011110243.GB4068@willie-the-truck>
Date:   Mon, 11 Oct 2021 12:02:44 +0100
From:   Will Deacon <will@...nel.org>
To:     Marc Zyngier <maz@...nel.org>
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Mark Rutland <mark.rutland@....com>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Peter Shier <pshier@...gle.com>,
        Raghavendra Rao Ananta <rananta@...gle.com>,
        Ricardo Koller <ricarkol@...gle.com>,
        Oliver Upton <oupton@...gle.com>,
        Catalin Marinas <catalin.marinas@....com>,
        Linus Walleij <linus.walleij@...aro.org>,
        kernel-team@...roid.com
Subject: Re: [PATCH v3 00/17] clocksource/arm_arch_timer: Add basic ARMv8.6
 support

On Sun, Oct 10, 2021 at 12:42:49PM +0100, Marc Zyngier wrote:
> This is v3 of the series enabling ARMv8.6 support for timer subsystem,
> and was prompted by a discussion with Oliver around the fact that an
> ARMv8.6 implementation must have a 1GHz counter, which leads to a
> number of things to break in the timer code:
> 
> - the counter rollover can come pretty quickly as we only advertise a
>   56bit counter,
> - the maximum timer delta can be remarkably small, as we use the
>   countdown interface which is limited to 32bit...
> 
> Thankfully, there is a way out: we can compute the minimal width of
> the counter based on the guarantees that the architecture gives us,
> and we can use the 64bit comparator interface instead of the countdown
> to program the timer.
> 
> Finally, we start making use of the ARMv8.6 ECV features by switching
> accesses to the counters to a self-synchronising register, removing
> the need for an ISB. Hopefully, implementations will *not* just stick
> an invisible ISB there...
> 
> A side effect of the switch to CVAL is that XGene-1 breaks. I have
> added a workaround to keep it alive.
> 
> I have added Oliver's original patch[0] to the series and tweaked a
> couple of things. Blame me if I broke anything.
> 
> The whole things has been tested on Juno (sysreg + MMIO timers),
> XGene-1 (broken sysreg timers), FVP (FEAT_ECV, CNT*CTSS_EL0).

The arm64 bits look pretty good to me (I left some minor comments).

How do you want to merge this series? It would be nice to have the arch
bits in the arm64 tree, if possible, as we'll be tripping over the cpucaps
stuff otherwise.

Will