linux-kernel - Re: [PATCH v3 3/8] net: phy: Add BaseT1 auto-negotiation registers

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Date:   Tue, 12 Oct 2021 09:14:38 +0200
From:   Oleksij Rempel <o.rempel@...gutronix.de>
To:     alexandru.tachici@...log.com
Cc:     andrew@...n.ch, davem@...emloft.net, devicetree@...r.kernel.org,
        hkallweit1@...il.com, kuba@...nel.org,
        linux-kernel@...r.kernel.org, linux@...linux.org.uk,
        netdev@...r.kernel.org, robh+dt@...nel.org
Subject: Re: [PATCH v3 3/8] net: phy: Add BaseT1 auto-negotiation registers

On Mon, Oct 11, 2021 at 05:22:10PM +0300, alexandru.tachici@...log.com wrote:
> From: Alexandru Tachici <alexandru.tachici@...log.com>
> 
> Added BASE-T1 AN advertisement register (Registers 7.514, 7.515, and
> 7.516) and BASE-T1 AN LP Base Page ability register (Registers 7.517,
> 7.518, and 7.519).
> 
> Signed-off-by: Alexandru Tachici <alexandru.tachici@...log.com>
> ---
>  include/uapi/linux/mdio.h | 40 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
> index 8ae82fe3aece..58ac5cdf7eb4 100644
> --- a/include/uapi/linux/mdio.h
> +++ b/include/uapi/linux/mdio.h
> @@ -67,6 +67,14 @@
>  #define MDIO_AN_10GBT_STAT	33	/* 10GBASE-T auto-negotiation status */
>  #define MDIO_PMA_10T1L_STAT	2295	/* 10BASE-T1L PMA status */
>  #define MDIO_PCS_10T1L_CTRL	2278	/* 10BASE-T1L PCS control */
> +#define MDIO_AN_T1_CTRL		512	/* BASE-T1 AN control */
> +#define MDIO_AN_T1_STAT		513	/* BASE-T1 AN status */
> +#define MDIO_AN_T1_ADV_L	514	/* BASE-T1 AN advertisement register [15:0] */
> +#define MDIO_AN_T1_ADV_M	515	/* BASE-T1 AN advertisement register [31:16] */
> +#define MDIO_AN_T1_ADV_H	516	/* BASE-T1 AN advertisement register [47:32] */
> +#define MDIO_AN_T1_LP_L		517	/* BASE-T1 AN LP's base page register [15:0] */
> +#define MDIO_AN_T1_LP_M		518	/* BASE-T1 AN LP's base page register [31:16] */
> +#define MDIO_AN_T1_LP_H		519	/* BASE-T1 AN LP's base page register [47:32] */

Please use same wording as in the spec: "BASE-T1 AN LP Base Page ability
register".

>  /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
>  #define MDIO_PMA_LASI_RXCTRL	0x9000	/* RX_ALARM control */
> @@ -278,6 +286,38 @@
>  #define MDIO_PCS_10T1L_CTRL_LB		0x4000	/* Enable PCS level loopback mode */
>  #define MDIO_PCS_10T1L_CTRL_RESET	0x8000	/* PCS reset */
>  
> +/* BASE-T1 auto-negotiation advertisement register [15:0] */
> +#define MDIO_AN_T1_ADV_L_PAUSE_CAP	ADVERTISE_PAUSE_CAP
> +#define MDIO_AN_T1_ADV_L_PAUSE_ASYM	ADVERTISE_PAUSE_ASYM
> +#define MDIO_AN_T1_ADV_L_FORCE_MS	0x1000	/* Force Master/slave Configuration */
> +#define MDIO_AN_T1_ADV_L_REMOTE_FAULT	ADVERTISE_RFAULT
> +#define MDIO_AN_T1_ADV_L_ACK		ADVERTISE_LPACK
> +#define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ	ADVERTISE_NPAGE
> +
> +/* BASE-T1 auto-negotiation advertisement register [31:16] */
> +#define MDIO_AN_T1_ADV_M_B10L		0x4000	/* device is compatible with 10BASE-T1L */
> +#define MDIO_AN_T1_ADV_M_MST		0x0010	/* advertise master preference */

Hm.. MDIO_AN_T1_ADV_M_MST is T4 of Link codeword Base Page. The spec says:
"Transmitted Nonce Field (T[4:0]) is a 5-bit wide field whose lower 4
bits contains a random or pseudorandom number. A new value shall be
generated for each entry to the Ability Detect state"

Should we actually do it?

> +/* BASE-T1 auto-negotiation advertisement register [47:32] */
> +#define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ	0x1000	/* 10BASE-T1L High Level Transmit Request */
> +#define MDIO_AN_T1_ADV_H_10L_TX_HI	0x2000	/* 10BASE-T1L High Level Transmit Ability */
> +
> +/* BASE-T1 AN LP's base page register [15:0] */
> +#define MDIO_AN_T1_LP_L_PAUSE_CAP	LPA_PAUSE_CAP
> +#define MDIO_AN_T1_LP_L_PAUSE_ASYM	LPA_PAUSE_ASYM
> +#define MDIO_AN_T1_LP_L_FORCE_MS	0x1000	/* LP Force Master/slave Configuration */
> +#define MDIO_AN_T1_LP_L_REMOTE_FAULT	LPA_RFAULT
> +#define MDIO_AN_T1_LP_L_ACK		LPA_LPACK
> +#define MDIO_AN_T1_LP_L_NEXT_PAGE_REQ	LPA_NPAGE
> +
> +/* BASE-T1 AN LP's base page register [31:16] */
> +#define MDIO_AN_T1_LP_M_MST		0x0080	/* LP master preference */

0x0080 is A2 == 1000BASE-T1 ability. Not master preference (T4).

> +#define MDIO_AN_T1_LP_M_B10L		0x4000	/* LP is compatible with 10BASE-T1L */
> +
> +/* BASE-T1 AN LP's base page register [47:32] */
> +#define MDIO_AN_T1_LP_H_10L_TX_HI_REQ	0x1000	/* 10BASE-T1L High Level LP Transmit Request */
> +#define MDIO_AN_T1_LP_H_10L_TX_HI	0x2000	/* 10BASE-T1L High Level LP Transmit Ability */
> +
>  /* EEE Supported/Advertisement/LP Advertisement registers.
>   *
>   * EEE capability Register (3.20), Advertisement (7.60) and
> -- 
> 2.25.1
> 
> 

Regards,
Oleksij
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