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Message-Id: <20211012153432.2817285-1-guoren@kernel.org>
Date: Tue, 12 Oct 2021 23:34:31 +0800
From: guoren@...nel.org
To: guoren@...nel.org, anup@...infault.org, atish.patra@....com,
maz@...nel.org, tglx@...utronix.de, palmer@...belt.com
Cc: linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
Guo Ren <guoren@...ux.alibaba.com>,
Rob Herring <robh@...nel.org>,
Palmer Dabbelt <palmerdabbelt@...gle.com>
Subject: [PATCH V2 1/2] dt-bindings: update riscv plic compatible string
From: Guo Ren <guoren@...ux.alibaba.com>
Add the compatible string "thead,c9xx-plic" to the riscv plic
bindings to support SOCs with thead,c9xx processor cores.
Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
Cc: Rob Herring <robh@...nel.org>
Cc: Palmer Dabbelt <palmerdabbelt@...gle.com>
Cc: Anup Patel <anup@...infault.org>
Cc: Atish Patra <atish.patra@....com>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 08d5a57ce00f..202eb7666f9b 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -46,6 +46,7 @@ properties:
- enum:
- sifive,fu540-c000-plic
- canaan,k210-plic
+ - thead,c9xx-plic
- const: sifive,plic-1.0.0
reg:
--
2.25.1
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