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Message-Id: <1634234784-5359-1-git-send-email-pmaliset@codeaurora.org>
Date:   Thu, 14 Oct 2021 23:36:24 +0530
From:   Prasad Malisetty <pmaliset@...eaurora.org>
To:     sanm@...eaurora.org, agross@...nel.org, bjorn.andersson@...aro.org,
        robh+dt@...nel.org, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        vbadigan@...eaurora.org, manivannan.sadhasivam@...aro.org
Cc:     Prasad Malisetty <pmaliset@...eaurora.org>
Subject: [PATCH v2] arm64: dts: qcom: sc7280: Add pcie clock support

Add pcie clock phandle for sc7280 SoC and correct
The pcie_1_pipe-clk clock name as same as binding.

fix: ab7772de8 ("arm64: dts: qcom: SC7280: Add rpmhcc clock controller node")
Signed-off-by: Prasad Malisetty <pmaliset@...eaurora.org>
Reported-by: kernel test robot <lkp@...el.com>

---
This change is depends on the below patch series.
https://lkml.org/lkml/2021/10/7/841
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 39635da..78694c1 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -569,9 +569,10 @@
 			reg = <0 0x00100000 0 0x1f0000>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
-				 <0>, <0>, <0>, <0>, <0>, <0>;
+				 <0>, <&pcie1_lane 0>,
+				 <0>, <0>, <0>, <0>;
 			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
-				      "pcie_0_pipe_clk", "pcie_1_pipe-clk",
+				      "pcie_0_pipe_clk", "pcie_1_pipe_clk",
 				      "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
 				      "ufs_phy_tx_symbol_0_clk",
 				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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