linux-kernel - Re: [PATCH v2] arm64: dts: qcom: sc7280: Add pcie clock support

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Message-ID: <CAE-0n51PGVQ6GT7RMTQajEM54NLOUZBGPkVKmVaG1JV7Fgv9Ag@mail.gmail.com>
Date:   Thu, 21 Oct 2021 11:06:53 -0700
From:   Stephen Boyd <swboyd@...omium.org>
To:     Prasad Malisetty <pmaliset@...eaurora.org>, agross@...nel.org,
        bjorn.andersson@...aro.org, devicetree@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        manivannan.sadhasivam@...aro.org, robh+dt@...nel.org,
        sanm@...eaurora.org, vbadigan@...eaurora.org
Subject: Re: [PATCH v2] arm64: dts: qcom: sc7280: Add pcie clock support

Quoting Prasad Malisetty (2021-10-14 11:06:24)
> Add pcie clock phandle for sc7280 SoC and correct
> The pcie_1_pipe-clk clock name as same as binding.
>
> fix: ab7772de8 ("arm64: dts: qcom: SC7280: Add rpmhcc clock controller node")

This is wrong. Should be

Fixes: ab7772de8612 ("arm64: dts: qcom: SC7280: Add rpmhcc clock
controller node")

> Signed-off-by: Prasad Malisetty <pmaliset@...eaurora.org>
> Reported-by: kernel test robot <lkp@...el.com>
>
> ---
> This change is depends on the below patch series.
> https://lkml.org/lkml/2021/10/7/841

Why doesn't that patch update this clock cell then?

> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 39635da..78694c1 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -569,9 +569,10 @@
>                         reg = <0 0x00100000 0 0x1f0000>;
>                         clocks = <&rpmhcc RPMH_CXO_CLK>,
>                                  <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> -                                <0>, <0>, <0>, <0>, <0>, <0>;
> +                                <0>, <&pcie1_lane 0>,
> +                                <0>, <0>, <0>, <0>;
>                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
> -                                     "pcie_0_pipe_clk", "pcie_1_pipe-clk",
> +                                     "pcie_0_pipe_clk", "pcie_1_pipe_clk",

This can be split from the patch to fix just the name in one patch and
then add the pcie1_lane phandle in the next patch. That way new features
aren't being mixed together with the string fix.

>                                       "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
>                                       "ufs_phy_tx_symbol_0_clk",
>                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk";