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Message-ID: <BN9PR11MB543330751AD68F70E89BC0FA8CB89@BN9PR11MB5433.namprd11.prod.outlook.com>
Date: Thu, 14 Oct 2021 08:01:49 +0000
From: "Tian, Kevin" <kevin.tian@...el.com>
To: Jean-Philippe Brucker <jean-philippe@...aro.org>
CC: Jason Gunthorpe <jgg@...dia.com>,
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Subject: RE: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO
> From: Jean-Philippe Brucker <jean-philippe@...aro.org>
> Sent: Thursday, September 30, 2021 6:33 PM
>
> The PTE flags define whether the memory access is cache-coherent or not.
> * WB is cacheable (short for write-back cacheable. Doesn't matter here
> what OI or RWA mean.)
> * NC is non-cacheable.
>
> | Normal PCI access | No_snoop PCI access
> -------+-------------------+-------------------
> PTE WB | Cacheable | Non-cacheable
> PTE NC | Non-cacheable | Non-cacheable
This implies that PCI no-snoop supersedes PTE flags when it's supported
by the system?
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